ELF ( (�4 4 � � (� (�0� 0� � 8 8 �
�� qx 8 & ( Kr %� qcom,pakala qcom,pakala board-id ,default_process-pakala-1.0-adsp 6 � aliases @/soc/spmi_bus@c400000 J/soc/spmi_bus@c431000 soc T � clock-controller@100000 qcom,gcc-pakala qcom,cc-pakala � \ 0 @ P ` p � � � � � / B / B � `GCC_GPLL0_CM_PLL_TAYCAN_COMMON GCC_GPLL1_CM_PLL_TAYCAN_COMMON GCC_GPLL2_CM_PLL_TAYCAN_COMMON GCC_GPLL3_CM_PLL_TAYCAN_COMMON GCC_GPLL4_CM_PLL_TAYCAN_COMMON GCC_GPLL5_CM_PLL_TAYCAN_COMMON GCC_GPLL6_CM_PLL_TAYCAN_COMMON GCC_GPLL7_CM_PLL_TAYCAN_COMMON GCC_GPLL8_CM_PLL_TAYCAN_COMMON GCC_GPLL9_CM_PLL_TAYCAN_COMMON GCC_JBIST_CM_PLL_JBIST4_COMMON GCC_AHB2PHY_SWMAN GCC_AHB2PHY_BROADCAST_SWMAN GCC_CLK_CTL_REG GCC_RPU_RPUQ7_200_CL36L12_LE GCC_RPU_XPU4 j T clock-controller@1f40000 ( qcom,lpass_aon_cc-pakala qcom,cc-pakala P \� � � � �� � �` �p � &� 4 `TCSR_TCSR_REGS LPASS_QDSP6SS_PUB LPASS_QDSP6SS_QDSP6SS_QDSP6SSV79_CORE_CC_SWI LPASS_QDSP6SS_PLL_PLL_CM_PLL_TAYCAN_COMMON LPASS_QDSP6SS_QDSP6SSV79_CORE_CC_REG LPASS_AON_CC_PLL_CM_PLL_TAYCAN_COMMON LPASS_AON_CC_AHB2PHY_SWMAN LPASS_AON_CC_AHB2PHY_BROADCAST_SWMAN LPASS_AON_CC_LPASS_AON_CC_REG LPASS_LPI_TCM_REG j T � clock-controller@7700000 + qcom,lpass_aon_mx_cc-pakala qcom,cc-pakala \p p` pp p� � � `LPASS_AON_MX_CC_RO_PLL_CM_PLL_PONGO_COMMON LPASS_AON_MX_CC_AHB2PHY_SWMAN LPASS_AON_MX_CC_AHB2PHY_BROADCAST_SWMAN LPASS_AON_MX_CC_LPASS_AON_MX_CC_REG j T � clock-controller@6bc0000 * qcom,lpass_audio_cc-pakala qcom,cc-pakala 0 \� � � �` �p �� � `LPASS_AUDIO_CC_PLL_CM_PLL_ZONDA_COMMON LPASS_AUDIO_CC_DIG_PLL_CM_PLL_TAYCAN_COMMON LPASS_AUDIO_CC_LCC_PLL_CM_PLL_JBIST4_COMMON LPASS_AUDIO_CC_AHB2PHY_SWMAN LPASS_AUDIO_CC_AHB2PHY_BROADCAST_SWMAN LPASS_AUDIO_CC_LPASS_AUDIO_CC_REG j T � clock-controller@7b00000 ) qcom,lpass_core_cc-pakala qcom,cc-pakala 0 \� �` �p �� � 0 � � `LPASS_LPASS_CORE_CC_DIG_PLL_LPASS_CORE_CC_DIG_PLL_CM_PLL_TAYCAN_COMMON LPASS_LPASS_CORE_CC_LPASS_CORE_CC_AHB2PHY_SWMAN LPASS_LPASS_CORE_CC_LPASS_CORE_CC_AHB2PHY_BROADCAST_SWMAN LPASS_LPASS_CORE_CC_LPASS_CORE_CC_LPASS_CORE_CC_REG LPASS_HW_AF_CORE LPASS_CORE_GDSC j T � clock-controller@6e40000 * qcom,lpass_lpmla_cc-pakala qcom,cc-pakala \� �` �p � @ � `LPASS_LPMLA_CC_DIG_PLL_CM_PLL_TAYCAN_COMMON LPASS_LPMLA_CC_AHB2PHY_SWMAN LPASS_LPMLA_CC_AHB2PHY_BROADCAST_SWMAN LPASS_LPMLA_CC_LPASS_LPMLA_CC_REG j T � clock-controller@7a00000 qcom,scc-pakala qcom,cc-pakala \� `SSC_SCC_SCC_SCC_REG j T � cesta@7213000 ' qcom,lpass_cesta-pakala qcom,cc-pakala ( \!0 !4 !8 !X !_ @ `LPASS_CRMB LPASS_CRMB_PT LPASS_CRMC LPASS_CRMV LPASS_CRM_COMMON T � glink qcom,glink 0 w proc-info � xport-smem-config edge-01 � � @ � � � N edge-02 � � @ � � � N xport-qmp-config edge-01 �aop_adsp � � � � � ipc_router qcom,ipc_router proc-info 1adsp ; devcfg-glink-xals edge-01 >SMEM Hapss RIPCRTR Z b� k v � � � edge-02 >SMEM Hmpss RIPCRTR Z b� k v � � � devcfg-mhi-xals edge-01 >MHI Hwpss ~ 2 � 3 smp2p qcom,smp2p proc-info � � � smp2p-interrupts intr-01 � � � intr-02 � � � smem
qcom,smem
�CORE_TOP_CSR �� � 0 �
@
@ ipcc
qcom,ipcc ipcc@403000 qcom,ipcc-protocol \ @ � MPROC , y 7 < @ ! " # - . T � ipcc@441000 qcom,ipcc-protocol \ @ � COMPUTE_L0 , N 7 < @ ! " #
/ - . T � ipcc@481000 qcom,ipcc-protocol \ @ � COMPUTE_L1 , � 7 < @ ! " #
/ - . T � ipcc@4c1000 qcom,ipcc-protocol \ @ � PERIPH , � 7 ( @
! " # - T � ipcc@501000 qcom,ipcc-protocol \ @ � FENCE , � 7 \ @ ! " #
/ � � � � � � � � - . T � ipcc_legacy@6888004 \� T � ipcc_legacy_sdc qcom,ipcc-legacy O � � , 8 9 : ; V � @ pinctrl@f100000 ! qcom,pakala-pinctrl qcom,pinctrl \ � _ � f ; l | � � , > O V B u � � } P �summary directconn0 directconn1 directconn2 directconn3 directconn4 directconn5 � �GPIOINTADSP T � qup2_se0_l0 � T ( ibi_i3c_qup2_se0_sda � T * qup2_se0_l1 � T ) ibi_i3c_qup2_se0_scl � T + qup2_se0_l2 � T , qup2_se0_l3 � T - qup2_se1_l0 � T . ibi_i3c_qup2_se1_sda � T 0 qup2_se1_l1 � T / ibi_i3c_qup2_se1_scl � T 1 qup2_se1_l2 � T 2 qup2_se1_l3 � T 3 qup2_se2_l0 � T 4 ibi_i3c_qup2_se2_sda � T � qup2_se2_l1 � T 5 ibi_i3c_qup2_se2_scl � T � qup2_se2_l2 �
T 6 qup2_se3_l0 � T 8 ibi_i3c_qup2_se3_sda � T � qup2_se2_l6 � T � qup2_se3_l1 �
T 9 ibi_i3c_qup2_se3_scl �
T � qup2_se2_l4 �
T � qup2_se3_l2 � T : qup2_se2_l3 � T 7 qup2_se3_l3 � T ; qup2_se2_l5 � T � qup2_se4_l0 � T < qup2_se4_l1 � T = qup2_se4_l2 � T > qup2_se4_l3 � T ? qup2_se5_l0 � T @ qup2_se5_l1 � T A qup2_se5_l2 � T B qup2_se5_l3 � T C qup2_se5_l6 � T � qup2_se6_l0 � T D qup2_se6_l1 � T E qup2_se6_l2 � T F qup2_se6_l3 � T G qup2_se7_l0 � T H ibi_i3c_qup2_se7_sda � T J qup2_se7_l1 � T I ibi_i3c_qup2_se7_scl � T K qup2_se7_l2 � T L qup2_se7_l3 � T M qup1_se0_l0 � T ibi_i3c_qup1_se0_sda � T qup1_se0_l1 � ! T ibi_i3c_qup1_se0_scl � ! T qup1_se0_l2 � " T qup1_se0_l3 � # T qup1_se1_l0 � $ T ibi_i3c_qup1_se1_sda � $ T
qup1_se1_l1 � % T ibi_i3c_qup1_se1_scl � % T qup1_se1_l2 � & T qup1_se1_l3 � ' T
qup1_se2_l0 � ( T qup1_se2_l1 � ) T qup1_se2_l2 � * T qup1_se2_l3 � + T qup1_se3_l0 � , T qup1_se3_l1 � - T qup1_se3_l2 � . T qup1_se3_l3 � / T qup1_se4_l0 � 0 T ibi_i3c_qup1_se4_sda � 0 T qup1_se4_l1 � 1 T ibi_i3c_qup1_se4_scl � 1 T qup1_se4_l2 � 2 T qup1_se4_l3 � 3 T qup1_se5_l0 � 4 T qup1_se5_l1 � 5 T qup1_se5_l2 � 6 T qup1_se5_l3 � 7 T qup1_se6_l0 � 8 T qup1_se6_l1 � 9 T ! qup1_se6_l2 � : T " qup1_se6_l3 � ; T # qup1_se7_l0 � < T $ qup1_se7_l1 � = T % qup1_se7_l2 � > T & qup1_se7_l3 � ? T ' qup1_se2_l4 � � T � qup1_se2_l5 � � T � qup1_se2_l6 � � T � top_qup1_se0_i2c_active � �
�
T top_qup1_se0_i2c_sleep � � � T top_qup1_se0_i3c_active � �
�
T top_qup1_se0_i3c_sleep � �! �! T top_qup1_se0_i3c_ibi_active � �
�
T top_qup1_se0_i3c_ibi_sleep � �! �! T top_qup1_se0_spi_active � X X X X T top_qup1_se0_spi_sleep � � ! � ! � ! � ! T top_qup1_se0_uart_active � � � � � T top_qup1_se0_uart_sleep � � � � � T top_qup1_se1_i2c_active � �
�
T top_qup1_se1_i2c_sleep � � � T top_qup1_se1_i3c_active � �
�
T top_qup1_se1_i3c_sleep � �! �! T top_qup1_se1_i3c_ibi_active �
�
�
T top_qup1_se1_i3c_ibi_sleep �
�! �! T top_qup1_se1_spi_active � X X X
X T ! top_qup1_se1_spi_sleep � � ! � ! � !
� ! T " top_qup1_se1_uart_active � � � �
� T # top_qup1_se1_uart_sleep � � � �
� T $ top_qup1_se2_i2c_active � �
�
T % top_qup1_se2_i2c_sleep � � � T & top_qup1_se2_spi_active � X X X X T ' top_qup1_se2_spi_sleep � � ! � ! � ! � ! T ( top_qup1_se2_uart_active � � � � � T ) top_qup1_se2_uart_sleep � � � � � T * top_qup1_se3_i2c_active � �
�
T + top_qup1_se3_i2c_sleep � � � T , top_qup1_se3_spi_active � X X X X T - top_qup1_se3_spi_sleep � � ! � ! � ! � ! T . top_qup1_se3_uart_active � � � � � T / top_qup1_se3_uart_sleep � � � � � T 0 top_qup1_se4_i2c_active � �
�
T 1 top_qup1_se4_i2c_sleep � � � T 2 top_qup1_se4_i3c_active � �
�
T 3 top_qup1_se4_i3c_sleep � �! �! T 4 top_qup1_se4_i3c_ibi_active � �
�
T 5 top_qup1_se4_i3c_ibi_sleep � �! �! T 6 top_qup1_se4_spi_active � X X X X T 7 top_qup1_se4_spi_sleep � � ! � ! � ! � ! T 8 top_qup1_se4_uart_active � � � � � T 9 top_qup1_se4_uart_sleep � � � � � T : top_qup1_se5_i2c_active � �
�
T ; top_qup1_se5_i2c_sleep � � � T < top_qup1_se5_spi_active � X X X X T = top_qup1_se5_spi_sleep � � ! � ! � ! � ! T > top_qup1_se5_uart_active � � � � � T ? top_qup1_se5_uart_sleep � � � � � T @ top_qup1_se6_i2c_active � �
! �
T A top_qup1_se6_i2c_sleep � � ! � T B top_qup1_se6_spi_active � X !X "X #X T C top_qup1_se6_spi_sleep � � ! ! � ! " � ! # � ! T D top_qup1_se6_uart_active � � ! � " � # � T E top_qup1_se6_uart_sleep � � ! � " � # � T F top_qup1_se7_i2c_active � $ �
% �
T G top_qup1_se7_i2c_sleep � $ � % � T H top_qup1_se7_spi_active � $X %X &X 'X T I top_qup1_se7_spi_sleep � $ � ! % � ! & � ! ' � ! T J top_qup1_se7_uart_active � $ � % � & � ' � T K top_qup1_se7_uart_sleep � $ � % � & � ' � T L top_qup2_se0_i2c_active � ( �
) �
T M top_qup2_se0_i2c_sleep � ( � ) � T N top_qup2_se0_i3c_active � ( �
) �
T O top_qup2_se0_i3c_sleep � ( �! ) �! T P top_qup2_se0_i3c_ibi_active � * �
+ �
T Q top_qup2_se0_i3c_ibi_sleep � * �! + �! T R top_qup2_se0_spi_active � (X )X ,X -X T S top_qup2_se0_spi_sleep � ( � ! ) � ! , � ! - � ! T T top_qup2_se0_uart_active � ( � ) � , � - � T U top_qup2_se0_uart_sleep � ( � ) � , � - � T V top_qup2_se1_i2c_active � . �
/ �
T W top_qup2_se1_i2c_sleep � . � / � T X top_qup2_se1_i3c_active � . �
/ �
T Y top_qup2_se1_i3c_sleep � . �! / �! T Z top_qup2_se1_i3c_ibi_active � 0 �
1 �
T [ top_qup2_se1_i3c_ibi_sleep � 0 �! 1 �! T \ top_qup2_se1_spi_active � .X /X 2X 3X T ] top_qup2_se1_spi_sleep � . � ! / � ! 2 � ! 3 � ! T ^ top_qup2_se1_uart_active � . � / � 2 � 3 � T _ top_qup2_se1_uart_sleep � . � / � 2 � 3 � T ` top_qup2_se2_i2c_active � 4 �
5 �
T a top_qup2_se2_i2c_sleep � 4 � 5 � T b top_qup2_se2_spi_active � 4X 5X 6X 7X T c top_qup2_se2_spi_sleep � 4 � ! 5 � ! 6 � ! 7 � ! T d top_qup2_se2_uart_active � 4 � 5 � 6 � 7 � T e top_qup2_se2_uart_sleep � 4 � 5 � 6 � 7 � T f top_qup2_se3_i2c_active � 8 �
9 �
T g top_qup2_se3_i2c_sleep � 8 � 9 � T h top_qup2_se3_spi_active � 8X 9X :X ;X T i top_qup2_se3_spi_sleep � 8 � ! 9 � ! : � ! ; � ! T j top_qup2_se3_uart_active � 8 � 9 � : � ; � T k top_qup2_se3_uart_sleep � 8 � 9 � : � ; � T l top_qup2_se4_i2c_active � < �
= �
T m top_qup2_se4_i2c_sleep � < � = � T n top_qup2_se4_spi_active � <X =X >X ?X T o top_qup2_se4_spi_sleep � < � ! = � ! > � ! ? � ! T p top_qup2_se4_uart_active � < � = � > � ? � T q top_qup2_se4_uart_sleep � < � = � > � ? � T r top_qup2_se5_i2c_active � @ �
A �
T s top_qup2_se5_i2c_sleep � @ � A � T t top_qup2_se5_spi_active � @X AX BX CX T u top_qup2_se5_spi_sleep � @ � ! A � ! B � ! C � ! T v top_qup2_se5_uart_active � @ � A � B � C � T w top_qup2_se5_uart_sleep � @ � A � B � C � T x top_qup2_se6_i2c_active � D �
E �
T y top_qup2_se6_i2c_sleep � D � E � T z top_qup2_se6_spi_active � DX EX FX GX T { top_qup2_se6_spi_sleep � D � ! E � ! F � ! G � ! T | top_qup2_se6_uart_active � D � E � F � G � T } top_qup2_se6_uart_sleep � D � E � F � G � T ~ top_qup2_se7_i2c_active � H �
I �
T top_qup2_se7_i2c_sleep � H � I � T � top_qup2_se7_i3c_active � H �
I �
T � top_qup2_se7_i3c_sleep � H �! I �! T � top_qup2_se7_i3c_ibi_active � J �
K �
T � top_qup2_se7_i3c_ibi_sleep � J �! K �! T � top_qup2_se7_spi_active � HX IX LX MX T � top_qup2_se7_spi_sleep � H � ! I � ! L � ! M � ! T � top_qup2_se7_uart_active � H � I � L � M � T � top_qup2_se7_uart_sleep � H � I � L � M � T � pinctrl@7760000 ! qcom,pakala-pinctrl qcom,pinctrl \v _ f ; � � \ � E E E E E E E E E E E E E E E E E E E E E E E T � slimbus_clk � T N slimbus_data � T O slimbus_default_gpio_cfg � N � ! O� ! T � pinctrl@75C0000 ! qcom,pakala-pinctrl qcom,pinctrl \\ _ - f ; l � � � � a a E E a a a a a a E E E E I E Q Q E E Q Q Q Q E E E E E E E E E E E E E E E E E E E E E T � ssc_qupv3_se0_0 � T P ssc_qupv3_se0_1 � T Q ssc_qupv3_se1_0 � T R ssc_qupv3_se1_1 � T S ssc_qupv3_se2_0 � T V ssc_qupv3_se2_1 � T W ssc_qupv3_se2_2 � T X ssc_qupv3_se4_4 � T � ssc_qupv3_se2_3 � T Y ssc_qupv3_se4_5 � T � ssc_qupv3_se3_0 � T Z ssc_qupv3_se2_4 � T � ssc_qupv3_se3_1 � T [ ssc_qupv3_se2_5 � T � ssc_qupv3_se4_0 �
T \ ssc_qupv3_se4_1 � T ] ssc_qupv3_se4_2 � T ^ ssc_qupv3_se4_3 �
T _ ssc_qupv3_se5_2 � T b ssc_qupv3_se5_0 � T ` ssc_qupv3_se1_2 � T T ssc_qupv3_se5_3 � T c ssc_qupv3_se5_1 � T a ssc_qupv3_se1_3 � T U ssc_qupv3_se6_0 � T d ssc_qupv3_se6_2 � T f ssc_qupv3_se10_2 � T r ssc_qupv3_se6_1 � T e ssc_qupv3_se6_3 � T g ssc_qupv3_se10_3 � T s ssc_qupv3_se7_2 � T j ssc_qupv3_se7_0 � T h ssc_qupv3_se7_3 � T k ssc_qupv3_se7_1 � T i ssc_qupv3_se8_0 � T l ssc_qupv3_se8_1 � T m ssc_qupv3_se9_0 � T n ssc_qupv3_se9_1 � T o ssc_qupv3_se10_0 � T p ssc_qupv3_se10_1 � T q ssc_qupv3_se11_0 � T t ssc_qupv3_se11_1 � T u ssc_qupv3_se11_2 � T v ssc_qupv3_se11_3 � T w ssc_qupv3_se12_0 � T x ssc_qupv3_se12_1 � T y ssc_qupv3_se13_0 � T z ssc_qupv3_se13_1 � ! T { ssc_qupv3_se13_2 � " T | ssc_qupv3_se13_3 � # T } ssc_qupv3_se14_0 � $ T ~ ssc_qupv3_se14_1 � % T qup_ssc0_se0_i2c_active � P �
Q �
T � qup_ssc0_se0_i2c_sleep � P � Q � T � qup_ssc0_se0_i3c_active � P �
Q �
T � qup_ssc0_se0_i3c_sleep � P � ! Q � ! T � qup_ssc0_se0_i3c_ibi_active � P �
Q �
T � qup_ssc0_se0_i3c_ibi_sleep � P � ! Q � ! T � qup_ssc0_se1_i2c_active � R �
S �
T � qup_ssc0_se1_i2c_sleep � R � S � T � qup_ssc0_se1_i3c_active � R �
S �
T � qup_ssc0_se1_i3c_sleep � R � ! S � ! T � qup_ssc0_se1_i3c_ibi_active � R �
S �
T � qup_ssc0_se1_i3c_ibi_sleep � R � ! S � ! T � qup_ssc0_se1_spi_active � RX SX TX UX T � qup_ssc0_se1_spi_sleep � R � ! S � ! T � ! U � ! T � qup_ssc0_se1_spi_3w_active � RX TX UX T � qup_ssc0_se1_spi_3w_sleep � R � ! T � ! U � ! T � qup_ssc0_se1_uart_active � R � S � T � U � T � qup_ssc0_se1_uart_sleep � R � S � T � U � T � qup_ssc0_se2_i2c_active � V �
W �
T � qup_ssc0_se2_i2c_sleep � V � W � T � qup_ssc0_se2_i3c_active � V �
W �
T � qup_ssc0_se2_i3c_sleep � V � ! W � ! T � qup_ssc0_se2_i3c_ibi_active � V �
W �
T � qup_ssc0_se2_i3c_ibi_sleep � V � ! W � ! T � qup_ssc0_se2_spi_active � VX WX XX YX T � qup_ssc0_se2_spi_sleep � V � ! W � ! X � ! Y � ! T � qup_ssc0_se2_spi_3w_active � VX XX YX T � qup_ssc0_se2_spi_3w_sleep � V � ! X � ! Y � ! T � qup_ssc0_se2_uart_active � V � W � X � Y � T � qup_ssc0_se2_uart_sleep � V � W � X � Y � T � qup_ssc0_se3_i2c_active � Z �
[ �
T � qup_ssc0_se3_i2c_sleep � Z � [ � T � qup_ssc0_se3_i3c_active � Z �
[ �
T � qup_ssc0_se3_i3c_sleep � Z � ! [ � ! T � qup_ssc0_se3_i3c_ibi_active � Z �
[ �
T � qup_ssc0_se3_i3c_ibi_sleep � Z � ! [ � ! T � qup_ssc0_se4_i2c_active � \ �
] �
T � qup_ssc0_se4_i2c_sleep � \ � ] � T � qup_ssc0_se4_spi_active � \X ]X ^X _X T � qup_ssc0_se4_spi_sleep � \ � ! ] � ! ^ � ! _ � ! T � qup_ssc0_se4_spi_3w_active � \X ^X _X T � qup_ssc0_se4_spi_3w_sleep � \ � ! ^ � ! _ � ! T � qup_ssc0_se4_uart_active � \ � ] � ^ � _ � T � qup_ssc0_se4_uart_sleep � \ � ] � ^ � _ � T � qup_ssc0_se5_i2c_active � ` �
a �
T � qup_ssc0_se5_i2c_sleep � ` � a � T � qup_ssc0_se5_i3c_active � ` �
a �
T � qup_ssc0_se5_i3c_sleep � ` � ! a � ! T � qup_ssc0_se5_i3c_ibi_active � ` �
a �
T � qup_ssc0_se5_i3c_ibi_sleep � ` � ! a � ! T � qup_ssc0_se5_spi_active � `X aX bX cX T � qup_ssc0_se5_spi_sleep � ` � ! a � ! b � ! c � ! T � qup_ssc0_se5_spi_3w_active � `X bX cX T � qup_ssc0_se5_spi_3w_sleep � ` � ! b � ! c � ! T � qup_ssc0_se5_uart_active � ` � a � b � c � T � qup_ssc0_se5_uart_sleep � ` � a � b � c � T � qup_ssc0_se6_i2c_active � d �
e �
T � qup_ssc0_se6_i2c_sleep � d � e � T � qup_ssc0_se6_i3c_active � d �
e �
T � qup_ssc0_se6_i3c_sleep � d � ! e � ! T � qup_ssc0_se6_i3c_ibi_active � d �
e �
T � qup_ssc0_se6_i3c_ibi_sleep � d � ! e � ! T � qup_ssc0_se6_spi_active � dX eX fX gX T � qup_ssc0_se6_spi_sleep � d � ! e � ! f � ! g � ! T � qup_ssc0_se6_spi_3w_active � dX fX gX T � qup_ssc0_se6_spi_3w_sleep � d � ! f � ! g � ! T � qup_ssc0_se6_uart_active � d � e � f � g � T � qup_ssc0_se6_uart_sleep � d � e � f � g � T � qup_ssc0_se7_i2c_active � h �
i �
T � qup_ssc0_se7_i2c_sleep � h � i � T � qup_ssc0_se7_spi_active � hX iX jX kX T � qup_ssc0_se7_spi_sleep � h � ! i � ! j � ! k � ! T � qup_ssc0_se7_spi_3w_active � hX jX kX T � qup_ssc0_se7_spi_3w_sleep � h � ! j � ! k � ! T � qup_ssc0_se7_uart_active � h � i � j � k � T � qup_ssc0_se7_uart_sleep � h � i � j � k � T � qup_ssc0_se8_i2c_active � l �
m �
T � qup_ssc0_se8_i2c_sleep � l � m � T � qup_ssc0_se8_i3c_active � l �
m �
T � qup_ssc0_se8_i3c_sleep � l � ! m � ! T � qup_ssc0_se8_i3c_ibi_active � l �
m �
T � qup_ssc0_se8_i3c_ibi_sleep � l � ! m � ! T � qup_ssc0_se9_i2c_active � n �
o �
T � qup_ssc0_se9_i2c_sleep � n � o � T � qup_ssc0_se9_i3c_active � n �
o �
T � qup_ssc0_se9_i3c_sleep � n � ! o � ! T � qup_ssc0_se9_i3c_ibi_active � n �
o �
T � qup_ssc0_se9_i3c_ibi_sleep � n � ! o � ! T � qup_ssc0_se10_i2c_active � p �
q �
T � qup_ssc0_se10_i2c_sleep � p � q � T � qup_ssc0_se10_spi_active � pX qX rX sX T � qup_ssc0_se10_spi_sleep � p � ! q � ! r � ! s � ! T � qup_ssc0_se10_spi_3w_active � pX rX sX T � qup_ssc0_se10_spi_3w_sleep � p � ! r � ! s � ! T � qup_ssc0_se10_uart_active � p � q � r � s � T � qup_ssc0_se10_uart_sleep � p � q � r � s � T � qup_ssc0_se11_i2c_active � t �
u �
T � qup_ssc0_se11_i2c_sleep � t � u � T � qup_ssc0_se11_spi_active � tX uX vX wX T � qup_ssc0_se11_spi_sleep � t � ! u � ! v � ! w � ! T � qup_ssc0_se11_spi_3w_active � tX vX wX T � qup_ssc0_se11_spi_3w_sleep � t � ! v � ! w � ! T � qup_ssc0_se11_uart_active � t � u � v � w � T � qup_ssc0_se11_uart_sleep � t � u � v � w � T � qup_ssc0_se12_i2c_active � x �
y �
T � qup_ssc0_se12_i2c_sleep � x � y � T � qup_ssc0_se13_i2c_active � z �
{ �
T � qup_ssc0_se13_i2c_sleep � z � { � T � qup_ssc0_se13_i3c_active � z �
{ �
T qup_ssc0_se13_i3c_sleep � z � ! { � ! T qup_ssc0_se13_i3c_ibi_active � z �
{ �
T qup_ssc0_se13_i3c_ibi_sleep � z � ! { � ! T qup_ssc0_se13_spi_active � zX {X |X }X T qup_ssc0_se13_spi_sleep � z � ! { � ! | � ! } � ! T qup_ssc0_se13_spi_3w_active � zX |X }X T qup_ssc0_se13_spi_3w_sleep � z � ! | � ! } � ! T qup_ssc0_se13_uart_active � z � { � | � } � T qup_ssc0_se13_uart_sleep � z � { � | � } � T qup_ssc0_se14_i2c_active � ~ �
�
T
qup_ssc0_se14_i2c_sleep � ~ � � T qup_ssc0_se14_i3c_active � ~ �
�
T qup_ssc0_se14_i3c_sleep � ~ � ! � ! T
qup_ssc0_se14_i3c_ibi_active � ~ �
�
T qup_ssc0_se14_i3c_ibi_sleep � z � ! { � ! T timetick timer@68a2000 qcom,timetick \� �SystemTimer
$� T � timer@68a3000 qcom,timetick \�0 �WakeUpTimer
$� T � spmi_bus@c400000 qcom,spmi-pmic-arb \ @ P pmk8550@0 qcom,spmi-pmic \ � � T � spmi-vadc@92 qcom,spmi-vadc \ � / = A E J N � vadc_ch_cfg VPH_PWR XVPH_PWR ^ � d n u � O � � � VBATT XVBATT ^ � d n u � O � � � VBATT_2S XVBATT_2S ^ � d n u � O � � � VBATT_2S_MID
XVBATT_2S_MID ^ � d n u � O � � � CHG_TEMP XCHG_TEMP ^ d n u � O � � � � BATT_THERM XBATT_THERM ^ D d n u � O���� � � �� � � BATT_THERM_PU_10K XBATT_THERM_PU_10K ^ $ d n u � O���� � � ' � � BATT_THERM_PU_400K XBATT_THERM_PU_400K ^ d d n u � O���� � � � � � BATT_ID_OHMS
XBATT_ID_OHMS ^ E d n u � O � � �� � BATT_ID_OHMS_PU_10K XBATT_ID_OHMS_PU_10K ^ % d n u � O � � ' � BATT_ID_OHMS_PU_400K XBATT_ID_OHMS_PU_400K ^ e d n u � O � � � � CONN_THERM_PM_07 XCONN_THERM_PM_07 ^ G d n u � O���� � � �� � � USB_SNS_V_MV
XUSB_SNS_V_MV ^ d n u � O � � � USB_IN_I_MA_PM_07 XUSB_IN_I_MA_PM_07 ^ d n u � O � � � � VIN_MUX XVIN_MUX ^ d n u � O � � � IBATT_MA XIBATT_MA ^ � d n u � O � � � � IBATT2_MA
XIBATT2_MA ^ � d n u � O � � � � BATT2_THERM XBATT2_THERM ^ L d n u � O���� � � �� � � BATT2_THERM_PU_10K XBATT2_THERM_PU_10K ^ , d n u � O���� � � ' � � BATT2_THERM_PU_400K XBATT2_THERM_PU_400K ^ l d n u � O���� � � � � � BATT2_ID_OHMS XBATT2_ID_OHMS ^ K d n u � O � � �� � BATT2_ID_OHMS_PU_10K XBATT2_ID_OHMS_PU_10K ^ + d n u � O � � ' � BATT2_ID_OHMS_PU_400K XBATT2_ID_OHMS_PU_400K ^ k d n u � O � � � � USBC_MUX_OPEN XUSBC_MUX_OPEN ^ d n u � O � � � USBC_MUX_10K
XUSBC_MUX_10K ^ 3 d n u � O � � ' � USBC_MUX_100K XUSBC_MUX_100K ^ S d n u � O � � �� � USBC_MUX_400K XUSBC_MUX_400K ^ s d n u � O � � � � WLS_THERM
XWLS_THERM ^ M d n u � O���� � � �� � � ICHG_SMB_SMB_A XICHG_SMB_SMB_A ^ d n u � ( ) O � � � � ICHG_SMB_SMB_B XICHG_SMB_SMB_B ^ d n u � ( ) O � � � � IIN_SMB_SMB_A XIIN_SMB_SMB_A ^ d n u � ( ) O � � � � IIN_SMB_SMB_B XIIN_SMB_SMB_B ^ d n u � ( ) O � � � � SMB_TEMP_I_SMB_A XSMB_TEMP_I_SMB_A ^ d n u � O � � � � SMB_TEMP_I_SMB_B XSMB_TEMP_I_SMB_B ^ d n u � O � � � � vadc-avg-ch gpio-map sid7_amux4_gpio � � sid7_amux2_gpio � � sid7_amux3_gpio � � therm_table T � therm_tb1 � � @�x � -�� � �$ � �� � R� � Ȩ �� (l m %� 1� z� � % �� * 5` / �� 4 � 9 �� > �� C i� H V� M G| R ;` W 18 \ )h a "� f L k � p " u z �
\ � � �
� therm_tb2 � X � �$ @ 8 �( ѐ �H jL *h � x� �4 ƨ
0� �
�` b� \� � � �( �� MH vadc_ibatt_tb � ��������� N N usbin_i_tb � � S � chg_temp_tb � � ��ŀ S p� smb_itemp_tb � � ��$� S + smb_vtemp_tb � � ��� S I ichg_fb_tb � ��������9 S -� vadctm_meas_cfg � VPH_PWR XVPH_PWR ^ � � �� � O � � � ' VBATT XVBATT ^ � � �� � O � � � � VBATT_2S XVBATT_2S ^ � � �� � O � � � ' pm8550@1 qcom,spmi-pmic \ � � pm8550ve@3 qcom,spmi-pmic \ � � luminous@4 qcom,spmi-pmic \ � � pm8550vs@5 qcom,spmi-pmic \ � � pm8550ve@6 qcom,spmi-pmic \ � � pm8750bh@7 qcom,spmi-pmic \ � � pm8550ve@8 qcom,spmi-pmic \ � � pm8550vs@9 qcom,spmi-pmic \ � � pmr735d@a qcom,spmi-pmic \
� � pm8010@c qcom,spmi-pmic \ � � pm8010@d qcom,spmi-pmic \
� � spmi_bus@c431000 qcom,spmi-pmic-arb \ C P cxstmtrace@37000000 qcom,stmtrace \7 � lpistmtrace@7100000 qcom,stmtrace \ � @ cxstmcfg@10002000 qcom,stmcfg \ � lpistmcfg@10B43000 qcom,stmcfg \�0 � cxetb@10B05000 qcom,tmc \�P lpietb@10B45000 qcom,tmc \�P qdss � ( 8 � 0 J� � � L� � L � !_!_ S� c p tpath_lpi_tpda } � � � T � tpath_rscc_tpda } � � � T � tpath_audio_tpda } � � � T � tpath_lpi_stm } � � � T � tpath_lpi_etm } � � � T � tpath_stm } � � T � tpath_sdc_itm } � � T � tpath_lpi_noc } � � T � tpath_aon_cam_noc } � � T � tpath_aoc } � � T � tpath_swm_etm } � � T � funnel@10041000
qcom,tfunnel \ T � funnel@10B04000
qcom,tfunnel \�@ T � funnel@10B44000
qcom,tfunnel \�@ T � funnel@10B50000
qcom,tfunnel \� T � port_lpi_stm qcom,gts � } � port_lpi_etm qcom,gts � } � port_stm qcom,gts � } � port_sdc_itm qcom,gts � } � port_lpi_noc qcom,gts � } � port_aon_cam_noc qcom,gts � } � port_aoc qcom,gts �
} � port_swm_etm qcom,gts � } � tpdm@10B46000
qcom,tpdm \�` �lpass � � � � tpdm@10B52000
qcom,tpdm \� �lpi_rscc � � � � � tpdm@10B54000
qcom,tpdm \�@
�lpi_audio � � � � tpdm@10B34000
qcom,tpdm \�@ �ddr_lpi � � � � tpda@10B47000
qcom,tpda \�p
�lpass-lpi � } � T � tpda@10B53000
qcom,tpda \�0 �lpass-rscc 7 � } � T � tpda@10B55000
qcom,tpda \�P �lpass-audio 8 � } � T � tnoc@10B31000
qcom,tnoc � � \� * � �port_ddr_lpi_tnoc T � cti@10B41000 qcom,cti �lpass_lpi_cti_1 \� cti@10B42000 qcom,cti �lpass_lpi_cti_sdc_2 \� cti@10B51000 qcom,cti �lpass_lpi_cti_3 \� cti@10B35000 qcom,cti �ddr_lpi_cti_0 \�P qdss_lpi_csr@6EE0000 qcom,qdss_lpi_csr \� kernel_test_devices@0 \ interrupt-controller@10140000 test,interrupt-control \ � T device1@f101000 qcom,test,singleton Device region mapping with name \ ;device1 `test_reg_singleton , ] �int1 device2@1011000 qcom,test,singleton ! Device region mapping with index ;device2 \ , ^ �int2 device3@0 qcom,test,singleton Device with no region mapping ;device3 \ , _ �int3 device4@1 qcom,test,not_compatible Device not compatible ;device4 \ , `
�zero int4 device5@1010000 qcom,test,non_singleton Device region mapping with name \ ;device5 `test_reg_non_singleton systemcache@24800000 qcom,systemcache 8 \$� $� %� %� &� &� $` @ a `llcc0_base llcc1_base llcc2_base llcc3_base llcc_bcast_or_base llcc_bcast_and_base shrm_csr_base ! @ 1 > T � llc-island qcom,llc-island islands V�� island@c,ff800000 \ �� | _ ibi_ssc_0_cfg@7500000 qcom,ibi-controller \P d � k p G y ! �ok T � ibi_ssc_1_cfg@7510000 qcom,ibi-controller \Q d � k p f y �ok T � ibi_ssc_2_cfg@7520000 qcom,ibi-controller \R d � k p � y �ok T � ibi_ssc_3_cfg@7530000 qcom,ibi-controller \S d � k p � y � �ok T � ibi_ssc_4_cfg@7540000 qcom,ibi-controller \T d � k p � y � �ok T � ibi_ssc_5_cfg@7550000 qcom,ibi-controller \U d � k p � y � �ok T � ibi_ssc_6_cfg@7560000 qcom,ibi-controller \V d � k p � y � �ok T � ibi_ssc_7_cfg@7570000 qcom,ibi-controller \W d � k p � y � �ok T � ibi_ssc_8_cfg@7580000 qcom,ibi-controller \X d � k p � y � �ok T � ibi_ssc_9_cfg@7590000 qcom,ibi-controller \Y d � k p � y � �ok T � ibi_top_0_cfg@EC90000 qcom,ibi-controller \� d � k p y = �ok T � ibi_top_1_cfg@ECA0000 qcom,ibi-controller \� d � k p ! y > �ok T � ibi_top_2_cfg@ECB0000 qcom,ibi-controller \� d � k p # y ? �ok T � ibi_top_3_cfg@ECC0000 qcom,ibi-controller \� d � k p % y @ �ok T � ibi_top_4_cfg@ECD0000 qcom,ibi-controller \� d � k p 0 y A �ok T � ibi_top_5_cfg@ECE0000 qcom,ibi-controller \� d � k p 2 y B �ok T � gsi_info qcom,gsi-controller gsi_qup_0 � � � � @ � � � � gsi_qup_1 � �@ ��� � � [ @ � � � � gsi_qup_2 � �@ ��� � � d @ � � � � gsi_ssc_qup_0 ��@ � � � @ � ! " # $ % & ' ( � � � ssc_pwr_domains qcom,ssc-pwr-domain-controller �ssc_gdsc � �@��H SSC_QUP_0@7900000 qcom,sscqup-controller \� �core2x core s-ahb m-ahb � �Sd� �d�4 ���v ��^�, � � � �р % / 6
�ok SSC_QUP_0_SE_0 qcom,se-controller D P ] f o y� � : �� � � �+ � � � � � � � � �se-clk � �H� J !i2c-default i2c-sleep i3c-default i3c-sleep i3c_ibi-default i3c_ibi-sleep / � 9 � C � M � W � a � �ok SSC_QUP_0_SE_1 qcom,se-controller D @ P ] f o y� � :�� � � �, � p � � � � � � �se-clk � � �Ǟ � !i2c-default i2c-sleep i3c-default i3c-sleep i3c_ibi-default i3c_ibi-sleep spi-default spi-sleep uart-default uart-sleep spi-3w-default spi-3w-sleep / � 9 � C � M � W � a � k � u � � � � � � � � �ok SSC_QUP_0_SE_2 qcom,se-controller D � P ] f o y� � :�� � � �- � @ � � � � � � � �se-clk � �~E: � !i2c-default i2c-sleep i3c-default i3c-sleep i3c_ibi-default i3c_ibi-sleep spi-default spi-sleep uart-default uart-sleep spi-3w-default spi-3w-sleep / � 9 � C � M � W � a � k � u � � � � � � � � �ok SSC_QUP_0_SE_3 qcom,se-controller D � P ] f o y� � :�� � � �. � B � � � � � � �se-clk � �� �w J !i2c-default i2c-sleep i3c-default i3c-sleep i3c_ibi-default i3c_ibi-sleep / � 9 � C � M � W � a � �ok SSC_QUP_0_SE_4 qcom,se-controller D P� ] f o y � :�� � � �/ � � � � � � � � � �se-clk � �*̉ ` !i2c-default i2c-sleep spi-default spi-sleep uart-default uart-sleep spi-3w-default spi-3w-sleep / � 9 � C � M � W � a � k � u � �ok SSC_QUP_0_SE_5 qcom,se-controller D @ P ] f o y� � :�� � � �0 � E � � � � � � � �se-clk � ���� � !i2c-default i2c-sleep i3c-default i3c-sleep i3c_ibi-default i3c_ibi-sleep spi-default spi-sleep uart-default uart-sleep spi-3w-default spi-3w-sleep / � 9 � C � M � W � a � k � u � � � � � � � � �ok SSC_QUP_0_SE_6 qcom,se-controller D � P ] f o y� � :�� � � �1 � G � � � � � � � �se-clk � ��� � !i2c-default i2c-sleep i3c-default i3c-sleep i3c_ibi-default i3c_ibi-sleep spi-default spi-sleep uart-default uart-sleep spi-3w-default spi-3w-sleep / � 9 � C � M � W � a � k � u � � � � � � � � �ok SSC_QUP_0_SE_7 qcom,se-controller D � P� ] f o y � :�� � � �* � � � � � � � � � �se-clk � ��O�� ` !i2c-default i2c-sleep uart-default uart-sleep spi-default spi-sleep spi-3w-default spi-3w-sleep / � 9 � C � M � W � a � k � u � �ok SSC_QUP_0_SE_8 qcom,se-controller D P ] f o y� � :�� � � �) � � � � � � � �se-clk � �pP� J !i2c-default i2c-sleep i3c-default i3c-sleep i3c_ibi-default i3c_ibi-sleep / � 9 � C � M � W � a � �ok SSC_QUP_0_SE_9 qcom,se-controller D @ P ] f o y� � :�� � � �� � � � � � � � �se-clk � �& J !i2c-default i2c-sleep i3c-default i3c-sleep i3c_ibi-default i3c_ibi-sleep / � 9 � C � M � W � a � �ok SSC_QUP_0_SE_10 qcom,se-controller D � P� ] f
o y � : �� � � �� � � � � � � � � �se-clk � �� �� ` !i2c-default i2c-sleep spi-default spi-sleep uart-default uart-sleep spi-3w-default spi-3w-sleep / � 9 � C � M � W � a � k � u � �ok SSC_QUP_0_SE_11 qcom,se-controller D � P� ] f o y � :�� � � �� � � � � � � � �se-clk � �l� ` !i2c-default i2c-sleep spi-default spi-sleep uart-default uart-sleep spi-3w-default spi-3w-sleep / � 9 � C � M � W � a � � � � � �ok SSC_QUP_0_SE_12 qcom,se-controller D P� ] f o y� � :�� � � �� � � � � � � � �se-clk � ���~ !i2c-default i2c-sleep / � 9 � �ok SSC_QUP_0_SE_13 qcom,se-controller D @ P ] f
o y� � :�� � � �� � � � � � � � �se-clk � �'*ɥ � !i2c-default i2c-sleep i3c-default i3c-sleep i3c_ibi-default i3c_ibi-sleep spi-default spi-sleep uart-default uart-sleep spi-3w-default spi-3w-sleep / � 9 � C M W a k u � � � �ok SSC_QUP_0_SE_14 qcom,se-controller D � P ] f o y� � : �� � � �� � � � � � � � �se-clk � ��V�c J !i2c-default i2c-sleep i3c-default i3c-sleep i3c_ibi-default i3c_ibi-sleep /
9 C M
W a �ok TOP_QUP_1@a00000 qcom,qup-controller \ � �core2x core s-ahb m-ahb � �ۂ� @��� 4(�~ r�a� � � � �� % / �ok TOP_QUP_1_SE_0 qcom,se-controller D P ] 0 f o y� � :
� � � � � � � � � � B@ �se-clk � � > x !i2c-default i2c-sleep i3c-default i3c-sleep i3c_ibi-default i3c_ibi-sleep spi-default spi-sleep uart-default uart-sleep / 9 C M W a k u � �ok TOP_QUP_1_SE_1 qcom,se-controller D @ P ] 0 f o y� � : � � � � � � � � � � B@ �se-clk � ދڬ x !i2c-default i2c-sleep i3c-default i3c-sleep i3c_ibi-default i3c_ibi-sleep spi-default spi-sleep uart-default uart-sleep / 9 C M W a k ! u " # � $ �ok TOP_QUP_1_SE_2 qcom,se-controller D � P� ] 0 f o y � :
� � � � � � � � � � B@ �se-clk � E�4� D !i2c-default i2c-sleep spi-default spi-sleep uart-default uart-sleep / % 9 & C ' M ( W ) a * �ok TOP_QUP_1_SE_3 qcom,se-controller D � P� ] 0 f o y � : � � � � � � � � � � B@ �se-clk � l� � D !i2c-default i2c-sleep spi-default spi-sleep uart-default uart-sleep / + 9 , C - M . W / a 0 �ok TOP_QUP_1_SE_4 qcom,se-controller D P ] 0 f o y� � :
� � � � � � � � � � B@ �se-clk � *�KF x !i2c-default i2c-sleep i3c-default i3c-sleep i3c_ibi-default i3c_ibi-sleep spi-default spi-sleep uart-default uart-sleep / 1 9 2 C 3 M 4 W 5 a 6 k 7 u 8 9 � : �ok TOP_QUP_1_SE_5 qcom,se-controller D @ P� ] 0 f o y � : � � � � � � � � � � B@ �se-clk � �y� D !i2c-default i2c-sleep spi-default spi-sleep uart-default uart-sleep / ; 9 < C = M > W ? a @ �ok TOP_QUP_1_SE_6 qcom,se-controller D � P� ] 0 f o y � :
� � � � � � � � � � B@ �se-clk � o�&j D !i2c-default i2c-sleep spi-default spi-sleep uart-default uart-sleep / A 9 B C C M D W E a F �ok TOP_QUP_1_SE_7 qcom,se-controller D � P� ] 0 f o y � :
� � � � � � � � � � B@ �se-clk � �G5� D !i2c-default i2c-sleep spi-default spi-sleep uart-default uart-sleep / G 9 H C I M J W K a L �ok TOP_QUP_2@800000 qcom,qup-controller \ � �core2x core s-ahb m-ahb � p�i �_h� ��~t 0n�U � � � �� % / �ok TOP_QUP_2_SE_0 qcom,se-controller D P ] 0 f o y� � :
� � � � � � � � � � B@ �se-clk � b8� x !i2c-default i2c-sleep i3c-default i3c-sleep i3c_ibi-default i3c_ibi-sleep spi-default spi-sleep uart-default uart-sleep / M 9 N C O M P W Q a R k S u T U � V �ok TOP_QUP_2_SE_1 qcom,se-controller D @ P ] 0 f o y� � : � � � � � � � � � � B@ �se-clk � �'�� x !i2c-default i2c-sleep i3c-default i3c-sleep i3c_ibi-default i3c_ibi-sleep spi-default spi-sleep uart-default uart-sleep / W 9 X C Y M Z W [ a \ k ] u ^ _ � ` �ok TOP_QUP_2_SE_2 qcom,se-controller D � P� ] 0 f o y � :
� � � � � � � � � � B@ �se-clk � ��+ D !i2c-default i2c-sleep spi-default spi-sleep uart-default uart-sleep / a 9 b C c M d W e a f �ok TOP_QUP_2_SE_3 qcom,se-controller D � P� ] 0 f o y � : � � � � � � � � � � B@ �se-clk � �,y D !i2c-default i2c-sleep spi-default spi-sleep uart-default uart-sleep / g 9 h C i M j W k a l �ok TOP_QUP_2_SE_4 qcom,se-controller D P� ] 0 f o y � :
� � � � � � � � � � B@ �se-clk � y��~ D !i2c-default i2c-sleep spi-default spi-sleep uart-default uart-sleep / m 9 n C o M p W q a r �ok TOP_QUP_2_SE_5 qcom,se-controller D @ P� ] 0 f o y � : � � � � � � � � � � B@ �se-clk � �w�� D !i2c-default i2c-sleep spi-default spi-sleep uart-default uart-sleep / s 9 t C u M v W w a x �ok TOP_QUP_2_SE_6 qcom,se-controller D � P� ] 0 f o y � :
� � � � � � � � � � B@ �se-clk � #,�� D !i2c-default i2c-sleep spi-default spi-sleep uart-default uart-sleep / y 9 z C { M | W } a ~ �ok TOP_QUP_2_SE_7 qcom,i2c-controller D � P ] 0 f o y� � :
� � � � � � � � � � B@ �se-clk � �r � x !i2c-default i2c-sleep i3c-default i3c-sleep i3c_ibi-default i3c_ibi-sleep spi-default spi-sleep uart-default uart-sleep / 9 � C � M � W � a � k � u � � � � �ok qup_tcsr_info qcom,quptcsr-controller � tcsr_cfg0 � j � ���( ���$ tcsr_cfg1 � k � ���0 ���, tcsr_cfg2 � � � ���8 ���4 SlimbusBSP qcom,smbus-controller � �SLIMBUS � � LPASS � � )�@ 1 8 B H 2 R B !slimbus-default / � ] i x � sb_0_DeviceProps �� � � � sb_1_DeviceProps �� � � � sb_2_DeviceProps �� � � � sb_3_DeviceProps �� � � � sb_4_DeviceProps �� � � � sb_5_DeviceProps �� � � sb_6_DeviceProps �� � � slimbus_gen_config_1 � �LPASS �/vcs/vdd_lpi_cx � � � �
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pd_mon audio_process qcom,pd_mon_user_process_config �/ramfs/audio_lpai.mbn 3 /rfs/root/vendor/firmware_mnt/image/audio_lpai.mbn audio_process " 6 � Iaudio_pd oem_process qcom,pd_mon_user_process_config �/ramfs/qdsp6_oemsw.mbn 4 /rfs/root/vendor/firmware_mnt/image/qdsp6_oemsw.mbn oem_process " 6 Ioem_pd charger_process qcom,pd_mon_user_process_config � charger_process " 6 � Icharger_pd qsh_process qcom,pd_mon_user_process_config �/ramfs/qsh.mbn , /rfs/root/vendor/firmware_mnt/image/qsh.mbn qsh_process " 6 �
Isensor_pd ois_process qcom,pd_mon_user_process_config �/ramfs/ois_lpai.mbn , /rfs/root/vendor/firmware_mnt/image/ois.mbn ois_process " 6 � Iois_pd pd_mon_restart qcom,pd_mon_restart X n rcinit qcom,rcinit_cfg rcinit_config_spinor � � �d � u0 � � � � � # � ? � [ � w � � rcinit_config � � !4 � � � � � � � # � ? � [ � w � � servreg
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! � ! !8 � !P � !e 2 !y !� !� !� @ !� !� " � " "' "> � "L � "k < "� "� "� "� � "� � # #0K #I #a� #s � #� #� #�d #� #� $ $- $F $b $z $� $� � $� $� % % %4 %M @ %j < %� %�Z %� %�QURTOS_ISLAND_POOL %�QURTOS_ISLAND_POOL diagcfg_early_log & & _ &1 � � � � &G diagcfg_f3_trace &_ &u � &� dal qcom,dal &� qdsp_pm config qcom,config_data &� &� &� lpassRegRange &�� &� � l2ConfigRegRange &� &� � cores-array core0 &� e ' ' '# ': ? 'P core1 &� f ' ' '# ': 'P core2 &� g ' ' '# ': " 'P core3 &� h ' ' '# ': 'P core4 &� i ' ' '# ': 'P core5 &� j ' ' X '# ': 'P core6 &� l ' ' '# ': ! 'P core7 &� m ' ' S '# ': 'P core8 &� o ' ' '# ': . 'P core9 &� { ' ' '# ': 2 'P core10 &� r ' ' '# ': + 'P core11 &� v ' ' '#
': / 'P core12 &� w ' ' ] '# ': 'P core13 &� y ' ' '# ': 1 'P core14 &� z ' ' '# ': 0 'P core15 &� | ' ' n o '# ': 6 7 'P core16 &� � ' ' j '# ': 'P core17 &� � ' ' m '# ': 'P core18 &� � ' ' k '# ': 'P core19 &� � ' ' l '# ': 5 'P memories-array memory0 '] ' memory1 '] ' clocks-array clock0 'c 'i 'q '}/clk/cpu '� '� ' clock1 'c 'i 'q '}lpass_core_cc_core_clk '� '� ' clock2 'c 'i 'q '}lpass_audio_cc_bus_clk '� '� ' clock3 'c 'i 'q '}lpass_aon_cc_aon_h_clk '� '� ' clock4 'c 6 'i 'q '}lpass_aon_cc_lpi_noc_ls_clk '� '� ' clock5 'c 7 'i 'q '}lpass_aon_cc_lpi_noc_hs_clk '� '� ' clock6 'c 'i 'q '}lpass_audio_cc_slimbus_core_clk '� '� ' clock7 'c 'i 'q '}lpass_core_cc_lpm_core_clk '� '� ' clock8 'c 'i 'q '}lpass_core_cc_lpm_mem0_core_clk '� '� ' clock9 'c 'i 'q '}lpass_audio_cc_codec_mem_clk '� '� ' clock10 'c 'i 'q '}lpass_audio_cc_codec_mem0_clk '� '� ' clock11 'c 'i 'q '}lpass_audio_cc_codec_mem1_clk '� '� ' clock12 'c 'i 'q '}lpass_audio_cc_codec_mem2_clk '� '� ' clock13 'c 'i 'q '}lpass_audio_cc_codec_mem3_clk '� '� ' clock14 'c 'i 'q '}lpass_aon_mx_cc_va_mem0_clk '� '� ' clock15 'c 'i 'q '}lpass_aon_mx_cc_va_mem1_clk '� '� ' clock16 'c 'i 'q $ '}lpass_core_cc_sysnoc_mport_core_clk '� '� ' clock17 'c 'i 'q '}lpass_audio_cc_bus_timeout_clk '� '� ' clock18 'c C 'i 'q ( '}lpass_aon_cc_lpass_0_lpmla_ahb_odsc_clk '� '� ' clock19 'c D 'i 'q ( '}lpass_aon_cc_lpass_1_lpmla_ahb_odsc_clk '� '� ' clock20 'c 'i 'q # '}lpass_core_cc_sysnoc_sway_core_clk '� '� ' clock21 'c ? 'i 'q '}scc_ccd_ahb2ahb_m_clk '� '� ' clock22 'c @ 'i 'q '}scc_ccd_ahb2ahb_s_clk '� '� ' clock23 'c A 'i 'q '}scc_ahb2ahb_s_clk '� '� ' clock24 'c B 'i 'q '}lpass_aon_mx_cc_ibi_clk '� '� ' clock25 'c S 'i 'q '}lpass_core_cc_resampler_clk '� '� ' clock26 'c X 'i 'q '}lpass_audio_cc_slimbus_clk '� '� ' clock27 'c Z 'i 'q '}lpass_core_cc_avsync_stc_clk '� '� ' clock28 'c [ 'i 'q '}lpass_core_cc_avsync_atime_clk '� '� ' clock29 'c ] 'i 'q '}lpass_core_cc_hw_af_clk '� '� ' clock30 'c ^ 'i 'q '}lpass_core_cc_hw_af_noc_clk '� '� ' clock31 'c n 'i 'q ! '}lpass_lpmla_cc_lpass_0_lpmla_clk '� '� ' clock32 'c o 'i 'q ! '}lpass_lpmla_cc_lpass_1_lpmla_clk '� '� ' clock33 'c t 'i 'q '}lpass_aon_cc_enpu_scheduler_clk '� '� ' clock34 'c j 'i 'q '}lpass_aon_cc_sdc_proc_fclk_clk '� '� ' clock35 'c m 'i 'q '}scc_ccd_clk '� '� ' clock36 'c l 'i 'q
'}scc_smem_clk '� '� ' busport-array busPort0 C '� '� '� '� '� busPort1 C '� @ '� '� '� '� busPort2 C A '� @ '� '� '� � '� busPort3 C B '� @ '� '� '� � '� busPort4 C C '� @ '� '� '� � '� busPort5 C D '� @ '� '� '� � '� busPort6 C E '� @ '� '� '� � '� busPort7 C '� '� '� '� � '� busPort8 C '� '� '� '� � '� busPort9 C '� '� '� '� � '� busPort10 C '� '� '� '� � '� busPort11 C '� @ '� '� '� � '� busPort12 C '� '� '� '� � '� busPort13 C
'� '� '� '� � '� busPort14 C '� @ '� ^ '� '� � '� busPort15 C '� '� '� '� � '� busPort16 C '� @ '� '� '� 1 '� busPort17 C '� @ '� '� '� 1 '� busPort18 C '� '� '� '� � '� busPort19 C '� '� '� '� � '� busPort20 C '� '� '� '� '� $ busPort21 C '� '� '� '� '� $ busPort22 C '� '� '� '� '� $ busPort23 C '� '� '� '� '� $ busPort24 C ! '� '� '� '� '� $ busPort25 C " '� '� '� '� '� $ busPort26 C $ '� � '� '� '� '� $ busPort27 C % '� � '� '� '� � '� $ busPort28 C ' '� � '� '� '� ' '� $ busPort29 C ( '� � '� '� '� '� $ busPort30 C + '� '� '� '� '� $ busPort31 C 1 '� '� '� '� '� $ busPort32 C 0 '� '� '� '� '� $ busPort33 C . '� '� '� '� '� $ busPort34 C 2 '� '� '� '� '� $ busPort35 C / '� '� '� '� '� $ busPort36 C 6 '� '� '� C '� '� $ busPort37 C 7 '� '� '� D '� '� $ busPort38 C 5 '� '� l '� '� � '� 5 busPort39 C ? '� '� '� '� '� ? extroute-array extBusRoute0 '� '� % extBusRoute1 '� A '� ( extBusRoute2 '� '� % extBusRoute3 '� B '� ( extBusRoute4 '� '� % extBusRoute5 '� C '� ( extBusRoute6 '� '� % extBusRoute7 '� D '� ( extBusRoute8 '� '� % extBusRoute9 '� E '� ( mipsroute-array mipsBwRoute0 '� '� % mipsBwRoute1 '� A '� ( pwrDomain-array pwrDomain0 ' '�/core/cpu/latency ( 'c ( (" (1 pwrDomain1 ' ! '�lpass_core_cc_lpass_core_hm_gdsc ( 'c ( (" (1 pwrDomain2 ' ! '�lpass_aon_cc_lpass_audio_hm_gdsc ( 'c ( (" (1 pwrDomain3 ' '� ( 'c ( (" (1 pwrDomain4 ' '�lpass_aon_cc_lpass_ssc_gdsc ( 'c ( (" (1 cestaBw-array client0 (@ (J (Qlpass path0 (] (k 5 cestaClk-array clk0 'c j '}lpass_aon_cc_sdc_proc_fclk_clk cestaPwrDomain-array pwrDomain0 ' '�lpass_aon_cc_lpass_ssc_gdsc features-array feature0 z (x � � � feature1 z (x � feature2 z (x � feature3 z (x �� � ��� feature4 z (x � feature5 z (x � feature6 z (x � feature7 z (x � feature8 z (x � � ��� feature9 z (x � ��� feature10 z (x 5�� � ��� feature11 z (x /�� � ��� feature12 z (x � feature13 z (x � � � feature14 z (x $=X � ��� feature15 z (x �� � '� feature16 z (x � feature17 z (x � feature18 z (x � feature19 z (x � feature20 z (x � feature21 z (x � feature22 z (x � feature23 z (x � feature24 z (x � feature25 z (x � feature26 z (x � feature27 z (x � feature28 z (x � feature29 z (x � ��� feature30 z (x � feature31 z (x � feature32 z (x � feature33 z (x � feature34 z (x � feature35 z (x � feature36 z (x � feature37 z (x � config_arch qcom,config_arch compensatedDdrBwTable 0 (| �� rp� � 0 (� �� ��� � 0 (� ܓ� ��� X 0 (� �t� �2� � 0 (� �U� �2� � 0 (� &�6� �� � 0 (� ,�� s�� � 0 (� 2��� �� � 0 (� 8�ـ �� � 0 (� >��� �� � 0 (�������� �� � adspsnocVoteTable 8 (| �� ��� � � ' 8 (� �� ��� � � ' 8 (� ܓ� ��� X X ' 8 (� �t� �2� � � ' 8 (� �U� e�� � � ' 8 (� &�6� �O� � � ' 8 (� ,�� �� � � ' 8 (� 2��� �� � � ' 8 (� 8�ـ �U� � � ' 8 (� >��� *�� � � ' 8 (�������� ��� � � ' compensatedLecDdrBwTable 0 (| �� ��� X 0 (� �� �2� � 0 (� � �� � 0 (� ׄ s�� � 0 (� �e �� � 0 (�������� �� � adspLecsnocVoteTable 8 (| �� ��� X 8 (� �� �2� � 8 (� � �O� � 8 (� ׄ �� � 8 (� �e �U� � 8 (�������� ��� � compensatedMlDdrBwTable 0 (| �� rp� X 0 (� kI� ��� � 0 (� Н� �2� � 0 (� 8� �� � 0 (� G�W s�� � 0 (� �n! �� � 0 (�������� �� � adspMlsnocVoteTable 8 (| �� ��� X 8 (� kI� ��� � 8 (� Н� �2� � 8 (� 8� �O� � 8 (� G�W �� � 8 (� �n! �U� � 8 (�������� ��� � adspToLpiNocFreqTable (| �0 $� (�$� 5 (�3� � (�=�P O� (�M�� j (�bkP $� mlToLpiNocFreqTable (|$� $� (�O� 5 (�RH � (� O� (�&�� j (�0� $� systemcache qcom,systemcache-sw (� � (� @ (� # - . llc-lpi-dump qcom,llc-lpi-dump 4 (�QSH_ISLAND_POOL SSC_ISLAND_POOL QSHTECH_ISLAND_POOL __symbols__ �/soc (�/soc/clock-controller@100000 (�/soc/clock-controller@1f40000 )/soc/clock-controller@7700000 )/soc/clock-controller@6bc0000 )$/soc/clock-controller@7b00000 )2/soc/clock-controller@6e40000 )A/soc/clock-controller@7a00000 )E/soc/cesta@7213000 )Q/soc/ipcc/ipcc@403000 )\/soc/ipcc/ipcc@441000 )l/soc/ipcc/ipcc@481000 )|/soc/ipcc/ipcc@4c1000 )�/soc/ipcc/ipcc@501000 )�/soc/ipcc_legacy@6888004 )�/soc/pinctrl@f100000 ! )�/soc/pinctrl@f100000/qup2_se0_l0 * )�/soc/pinctrl@f100000/ibi_i3c_qup2_se0_sda ! )�/soc/pinctrl@f100000/qup2_se0_l1 * )�/soc/pinctrl@f100000/ibi_i3c_qup2_se0_scl ! )�/soc/pinctrl@f100000/qup2_se0_l2 ! )�/soc/pinctrl@f100000/qup2_se0_l3 ! )�/soc/pinctrl@f100000/qup2_se1_l0 * *
/soc/pinctrl@f100000/ibi_i3c_qup2_se1_sda ! * /soc/pinctrl@f100000/qup2_se1_l1 * *+/soc/pinctrl@f100000/ibi_i3c_qup2_se1_scl ! *@/soc/pinctrl@f100000/qup2_se1_l2 ! *L/soc/pinctrl@f100000/qup2_se1_l3 ! *X/soc/pinctrl@f100000/qup2_se2_l0 * *d/soc/pinctrl@f100000/ibi_i3c_qup2_se2_sda ! *y/soc/pinctrl@f100000/qup2_se2_l1 * *�/soc/pinctrl@f100000/ibi_i3c_qup2_se2_scl ! *�/soc/pinctrl@f100000/qup2_se2_l2 ! *�/soc/pinctrl@f100000/qup2_se3_l0 * *�/soc/pinctrl@f100000/ibi_i3c_qup2_se3_sda ! *�/soc/pinctrl@f100000/qup2_se2_l6 ! *�/soc/pinctrl@f100000/qup2_se3_l1 * *�/soc/pinctrl@f100000/ibi_i3c_qup2_se3_scl ! *�/soc/pinctrl@f100000/qup2_se2_l4 ! + /soc/pinctrl@f100000/qup2_se3_l2 ! + /soc/pinctrl@f100000/qup2_se2_l3 ! +/soc/pinctrl@f100000/qup2_se3_l3 ! +$/soc/pinctrl@f100000/qup2_se2_l5 ! +0/soc/pinctrl@f100000/qup2_se4_l0 ! +</soc/pinctrl@f100000/qup2_se4_l1 ! +H/soc/pinctrl@f100000/qup2_se4_l2 ! +T/soc/pinctrl@f100000/qup2_se4_l3 ! +`/soc/pinctrl@f100000/qup2_se5_l0 ! +l/soc/pinctrl@f100000/qup2_se5_l1 ! +x/soc/pinctrl@f100000/qup2_se5_l2 ! +�/soc/pinctrl@f100000/qup2_se5_l3 ! +�/soc/pinctrl@f100000/qup2_se5_l6 ! +�/soc/pinctrl@f100000/qup2_se6_l0 ! +�/soc/pinctrl@f100000/qup2_se6_l1 ! +�/soc/pinctrl@f100000/qup2_se6_l2 ! +�/soc/pinctrl@f100000/qup2_se6_l3 ! +�/soc/pinctrl@f100000/qup2_se7_l0 * +�/soc/pinctrl@f100000/ibi_i3c_qup2_se7_sda ! +�/soc/pinctrl@f100000/qup2_se7_l1 * +�/soc/pinctrl@f100000/ibi_i3c_qup2_se7_scl ! ,/soc/pinctrl@f100000/qup2_se7_l2 ! ,/soc/pinctrl@f100000/qup2_se7_l3 ! ,&/soc/pinctrl@f100000/qup1_se0_l0 * ,2/soc/pinctrl@f100000/ibi_i3c_qup1_se0_sda ! ,G/soc/pinctrl@f100000/qup1_se0_l1 * ,S/soc/pinctrl@f100000/ibi_i3c_qup1_se0_scl ! ,h/soc/pinctrl@f100000/qup1_se0_l2 ! ,t/soc/pinctrl@f100000/qup1_se0_l3 ! ,�/soc/pinctrl@f100000/qup1_se1_l0 * ,�/soc/pinctrl@f100000/ibi_i3c_qup1_se1_sda ! ,�/soc/pinctrl@f100000/qup1_se1_l1 * ,�/soc/pinctrl@f100000/ibi_i3c_qup1_se1_scl ! ,�/soc/pinctrl@f100000/qup1_se1_l2 ! ,�/soc/pinctrl@f100000/qup1_se1_l3 ! ,�/soc/pinctrl@f100000/qup1_se2_l0 ! ,�/soc/pinctrl@f100000/qup1_se2_l1 ! ,�/soc/pinctrl@f100000/qup1_se2_l2 ! ,�/soc/pinctrl@f100000/qup1_se2_l3 ! -
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9�/soc/pinctrl@7760000/slimbus_clk " 9�/soc/pinctrl@7760000/slimbus_data . 9�/soc/pinctrl@7760000/slimbus_default_gpio_cfg 9�/soc/pinctrl@75C0000 % 9�/soc/pinctrl@75C0000/ssc_qupv3_se0_0 % 9�/soc/pinctrl@75C0000/ssc_qupv3_se0_1 % : /soc/pinctrl@75C0000/ssc_qupv3_se1_0 % :/soc/pinctrl@75C0000/ssc_qupv3_se1_1 % : /soc/pinctrl@75C0000/ssc_qupv3_se2_0 % :0/soc/pinctrl@75C0000/ssc_qupv3_se2_1 % :@/soc/pinctrl@75C0000/ssc_qupv3_se2_2 % :P/soc/pinctrl@75C0000/ssc_qupv3_se4_4 % :`/soc/pinctrl@75C0000/ssc_qupv3_se2_3 % :p/soc/pinctrl@75C0000/ssc_qupv3_se4_5 % :�/soc/pinctrl@75C0000/ssc_qupv3_se3_0 % :�/soc/pinctrl@75C0000/ssc_qupv3_se2_4 % :�/soc/pinctrl@75C0000/ssc_qupv3_se3_1 % :�/soc/pinctrl@75C0000/ssc_qupv3_se2_5 % :�/soc/pinctrl@75C0000/ssc_qupv3_se4_0 % :�/soc/pinctrl@75C0000/ssc_qupv3_se4_1 % :�/soc/pinctrl@75C0000/ssc_qupv3_se4_2 % :�/soc/pinctrl@75C0000/ssc_qupv3_se4_3 % ; /soc/pinctrl@75C0000/ssc_qupv3_se5_2 % ;/soc/pinctrl@75C0000/ssc_qupv3_se5_0 % ; /soc/pinctrl@75C0000/ssc_qupv3_se1_2 % ;0/soc/pinctrl@75C0000/ssc_qupv3_se5_3 % ;@/soc/pinctrl@75C0000/ssc_qupv3_se5_1 % ;P/soc/pinctrl@75C0000/ssc_qupv3_se1_3 % ;`/soc/pinctrl@75C0000/ssc_qupv3_se6_0 % ;p/soc/pinctrl@75C0000/ssc_qupv3_se6_2 & ;�/soc/pinctrl@75C0000/ssc_qupv3_se10_2 % ;�/soc/pinctrl@75C0000/ssc_qupv3_se6_1 % ;�/soc/pinctrl@75C0000/ssc_qupv3_se6_3 & ;�/soc/pinctrl@75C0000/ssc_qupv3_se10_3 % ;�/soc/pinctrl@75C0000/ssc_qupv3_se7_2 % ;�/soc/pinctrl@75C0000/ssc_qupv3_se7_0 % ;�/soc/pinctrl@75C0000/ssc_qupv3_se7_3 % ;�/soc/pinctrl@75C0000/ssc_qupv3_se7_1 % </soc/pinctrl@75C0000/ssc_qupv3_se8_0 % </soc/pinctrl@75C0000/ssc_qupv3_se8_1 % <"/soc/pinctrl@75C0000/ssc_qupv3_se9_0 % <2/soc/pinctrl@75C0000/ssc_qupv3_se9_1 & <B/soc/pinctrl@75C0000/ssc_qupv3_se10_0 & <S/soc/pinctrl@75C0000/ssc_qupv3_se10_1 & <d/soc/pinctrl@75C0000/ssc_qupv3_se11_0 & <u/soc/pinctrl@75C0000/ssc_qupv3_se11_1 & <�/soc/pinctrl@75C0000/ssc_qupv3_se11_2 & <�/soc/pinctrl@75C0000/ssc_qupv3_se11_3 & <�/soc/pinctrl@75C0000/ssc_qupv3_se12_0 & <�/soc/pinctrl@75C0000/ssc_qupv3_se12_1 & <�/soc/pinctrl@75C0000/ssc_qupv3_se13_0 & <�/soc/pinctrl@75C0000/ssc_qupv3_se13_1 & <�/soc/pinctrl@75C0000/ssc_qupv3_se13_2 & <�/soc/pinctrl@75C0000/ssc_qupv3_se13_3 & =/soc/pinctrl@75C0000/ssc_qupv3_se14_0 & = /soc/pinctrl@75C0000/ssc_qupv3_se14_1 - =0/soc/pinctrl@75C0000/qup_ssc0_se0_i2c_active , =H/soc/pinctrl@75C0000/qup_ssc0_se0_i2c_sleep - =_/soc/pinctrl@75C0000/qup_ssc0_se0_i3c_active , =w/soc/pinctrl@75C0000/qup_ssc0_se0_i3c_sleep 1 =�/soc/pinctrl@75C0000/qup_ssc0_se0_i3c_ibi_active 0 =�/soc/pinctrl@75C0000/qup_ssc0_se0_i3c_ibi_sleep - =�/soc/pinctrl@75C0000/qup_ssc0_se1_i2c_active , =�/soc/pinctrl@75C0000/qup_ssc0_se1_i2c_sleep - =�/soc/pinctrl@75C0000/qup_ssc0_se1_i3c_active , > /soc/pinctrl@75C0000/qup_ssc0_se1_i3c_sleep 1 >#/soc/pinctrl@75C0000/qup_ssc0_se1_i3c_ibi_active 0 >?/soc/pinctrl@75C0000/qup_ssc0_se1_i3c_ibi_sleep - >Z/soc/pinctrl@75C0000/qup_ssc0_se1_spi_active , >r/soc/pinctrl@75C0000/qup_ssc0_se1_spi_sleep 0 >�/soc/pinctrl@75C0000/qup_ssc0_se1_spi_3w_active / >�/soc/pinctrl@75C0000/qup_ssc0_se1_spi_3w_sleep . >�/soc/pinctrl@75C0000/qup_ssc0_se1_uart_active - >�/soc/pinctrl@75C0000/qup_ssc0_se1_uart_sleep - >�/soc/pinctrl@75C0000/qup_ssc0_se2_i2c_active , ?/soc/pinctrl@75C0000/qup_ssc0_se2_i2c_sleep - ? /soc/pinctrl@75C0000/qup_ssc0_se2_i3c_active , ?6/soc/pinctrl@75C0000/qup_ssc0_se2_i3c_sleep 1 ?M/soc/pinctrl@75C0000/qup_ssc0_se2_i3c_ibi_active 0 ?i/soc/pinctrl@75C0000/qup_ssc0_se2_i3c_ibi_sleep - ?�/soc/pinctrl@75C0000/qup_ssc0_se2_spi_active , ?�/soc/pinctrl@75C0000/qup_ssc0_se2_spi_sleep 0 ?�/soc/pinctrl@75C0000/qup_ssc0_se2_spi_3w_active / ?�/soc/pinctrl@75C0000/qup_ssc0_se2_spi_3w_sleep . ?�/soc/pinctrl@75C0000/qup_ssc0_se2_uart_active - @/soc/pinctrl@75C0000/qup_ssc0_se2_uart_sleep - @/soc/pinctrl@75C0000/qup_ssc0_se3_i2c_active , @1/soc/pinctrl@75C0000/qup_ssc0_se3_i2c_sleep - @H/soc/pinctrl@75C0000/qup_ssc0_se3_i3c_active , @`/soc/pinctrl@75C0000/qup_ssc0_se3_i3c_sleep 1 @w/soc/pinctrl@75C0000/qup_ssc0_se3_i3c_ibi_active 0 @�/soc/pinctrl@75C0000/qup_ssc0_se3_i3c_ibi_sleep - @�/soc/pinctrl@75C0000/qup_ssc0_se4_i2c_active , @�/soc/pinctrl@75C0000/qup_ssc0_se4_i2c_sleep - @�/soc/pinctrl@75C0000/qup_ssc0_se4_spi_active , @�/soc/pinctrl@75C0000/qup_ssc0_se4_spi_sleep 0 A /soc/pinctrl@75C0000/qup_ssc0_se4_spi_3w_active / A'/soc/pinctrl@75C0000/qup_ssc0_se4_spi_3w_sleep . AA/soc/pinctrl@75C0000/qup_ssc0_se4_uart_active - AZ/soc/pinctrl@75C0000/qup_ssc0_se4_uart_sleep - Ar/soc/pinctrl@75C0000/qup_ssc0_se5_i2c_active , A�/soc/pinctrl@75C0000/qup_ssc0_se5_i2c_sleep - A�/soc/pinctrl@75C0000/qup_ssc0_se5_i3c_active , A�/soc/pinctrl@75C0000/qup_ssc0_se5_i3c_sleep 1 A�/soc/pinctrl@75C0000/qup_ssc0_se5_i3c_ibi_active 0 A�/soc/pinctrl@75C0000/qup_ssc0_se5_i3c_ibi_sleep - B/soc/pinctrl@75C0000/qup_ssc0_se5_spi_active , B /soc/pinctrl@75C0000/qup_ssc0_se5_spi_sleep 0 B6/soc/pinctrl@75C0000/qup_ssc0_se5_spi_3w_active / BQ/soc/pinctrl@75C0000/qup_ssc0_se5_spi_3w_sleep . Bk/soc/pinctrl@75C0000/qup_ssc0_se5_uart_active - B�/soc/pinctrl@75C0000/qup_ssc0_se5_uart_sleep - B�/soc/pinctrl@75C0000/qup_ssc0_se6_i2c_active , B�/soc/pinctrl@75C0000/qup_ssc0_se6_i2c_sleep - B�/soc/pinctrl@75C0000/qup_ssc0_se6_i3c_active , B�/soc/pinctrl@75C0000/qup_ssc0_se6_i3c_sleep 1 B�/soc/pinctrl@75C0000/qup_ssc0_se6_i3c_ibi_active 0 C/soc/pinctrl@75C0000/qup_ssc0_se6_i3c_ibi_sleep - C1/soc/pinctrl@75C0000/qup_ssc0_se6_spi_active , CI/soc/pinctrl@75C0000/qup_ssc0_se6_spi_sleep 0 C`/soc/pinctrl@75C0000/qup_ssc0_se6_spi_3w_active / C{/soc/pinctrl@75C0000/qup_ssc0_se6_spi_3w_sleep . C�/soc/pinctrl@75C0000/qup_ssc0_se6_uart_active - C�/soc/pinctrl@75C0000/qup_ssc0_se6_uart_sleep - C�/soc/pinctrl@75C0000/qup_ssc0_se7_i2c_active , C�/soc/pinctrl@75C0000/qup_ssc0_se7_i2c_sleep - C�/soc/pinctrl@75C0000/qup_ssc0_se7_spi_active , D
/soc/pinctrl@75C0000/qup_ssc0_se7_spi_sleep 0 D$/soc/pinctrl@75C0000/qup_ssc0_se7_spi_3w_active / D?/soc/pinctrl@75C0000/qup_ssc0_se7_spi_3w_sleep . DY/soc/pinctrl@75C0000/qup_ssc0_se7_uart_active - Dr/soc/pinctrl@75C0000/qup_ssc0_se7_uart_sleep - D�/soc/pinctrl@75C0000/qup_ssc0_se8_i2c_active , D�/soc/pinctrl@75C0000/qup_ssc0_se8_i2c_sleep - D�/soc/pinctrl@75C0000/qup_ssc0_se8_i3c_active , D�/soc/pinctrl@75C0000/qup_ssc0_se8_i3c_sleep 1 D�/soc/pinctrl@75C0000/qup_ssc0_se8_i3c_ibi_active 0 E/soc/pinctrl@75C0000/qup_ssc0_se8_i3c_ibi_sleep - E /soc/pinctrl@75C0000/qup_ssc0_se9_i2c_active , E7/soc/pinctrl@75C0000/qup_ssc0_se9_i2c_sleep - EN/soc/pinctrl@75C0000/qup_ssc0_se9_i3c_active , Ef/soc/pinctrl@75C0000/qup_ssc0_se9_i3c_sleep 1 E}/soc/pinctrl@75C0000/qup_ssc0_se9_i3c_ibi_active 0 E�/soc/pinctrl@75C0000/qup_ssc0_se9_i3c_ibi_sleep . E�/soc/pinctrl@75C0000/qup_ssc0_se10_i2c_active - E�/soc/pinctrl@75C0000/qup_ssc0_se10_i2c_sleep . E�/soc/pinctrl@75C0000/qup_ssc0_se10_spi_active - E�/soc/pinctrl@75C0000/qup_ssc0_se10_spi_sleep 1 F/soc/pinctrl@75C0000/qup_ssc0_se10_spi_3w_active 0 F2/soc/pinctrl@75C0000/qup_ssc0_se10_spi_3w_sleep / FM/soc/pinctrl@75C0000/qup_ssc0_se10_uart_active . Fg/soc/pinctrl@75C0000/qup_ssc0_se10_uart_sleep . F�/soc/pinctrl@75C0000/qup_ssc0_se11_i2c_active - F�/soc/pinctrl@75C0000/qup_ssc0_se11_i2c_sleep . F�/soc/pinctrl@75C0000/qup_ssc0_se11_spi_active - F�/soc/pinctrl@75C0000/qup_ssc0_se11_spi_sleep 1 F�/soc/pinctrl@75C0000/qup_ssc0_se11_spi_3w_active 0 F�/soc/pinctrl@75C0000/qup_ssc0_se11_spi_3w_sleep / G/soc/pinctrl@75C0000/qup_ssc0_se11_uart_active . G3/soc/pinctrl@75C0000/qup_ssc0_se11_uart_sleep . GL/soc/pinctrl@75C0000/qup_ssc0_se12_i2c_active - Ge/soc/pinctrl@75C0000/qup_ssc0_se12_i2c_sleep . G}/soc/pinctrl@75C0000/qup_ssc0_se13_i2c_active - G�/soc/pinctrl@75C0000/qup_ssc0_se13_i2c_sleep . G�/soc/pinctrl@75C0000/qup_ssc0_se13_i3c_active - G�/soc/pinctrl@75C0000/qup_ssc0_se13_i3c_sleep 2 G�/soc/pinctrl@75C0000/qup_ssc0_se13_i3c_ibi_active 1 G�/soc/pinctrl@75C0000/qup_ssc0_se13_i3c_ibi_sleep . H/soc/pinctrl@75C0000/qup_ssc0_se13_spi_active - H1/soc/pinctrl@75C0000/qup_ssc0_se13_spi_sleep 1 HI/soc/pinctrl@75C0000/qup_ssc0_se13_spi_3w_active 0 He/soc/pinctrl@75C0000/qup_ssc0_se13_spi_3w_sleep / H�/soc/pinctrl@75C0000/qup_ssc0_se13_uart_active . H�/soc/pinctrl@75C0000/qup_ssc0_se13_uart_sleep . H�/soc/pinctrl@75C0000/qup_ssc0_se14_i2c_active - H�/soc/pinctrl@75C0000/qup_ssc0_se14_i2c_sleep . H�/soc/pinctrl@75C0000/qup_ssc0_se14_i3c_active - H�/soc/pinctrl@75C0000/qup_ssc0_se14_i3c_sleep 2 I/soc/pinctrl@75C0000/qup_ssc0_se14_i3c_ibi_active 1 I2/soc/pinctrl@75C0000/qup_ssc0_se14_i3c_ibi_sleep IN/soc/timetick/timer@68a2000 IZ/soc/timetick/timer@68a3000 If/soc/spmi_bus@c400000/pmk8550@0 9 Il/soc/spmi_bus@c400000/pmk8550@0/spmi-vadc@92/therm_table Ix/soc/qdss/tpath_lpi_tpda I�/soc/qdss/tpath_rscc_tpda I�/soc/qdss/tpath_audio_tpda I�/soc/qdss/tpath_lpi_stm I�/soc/qdss/tpath_lpi_etm I�/soc/qdss/tpath_stm I�/soc/qdss/tpath_sdc_itm I�/soc/qdss/tpath_lpi_noc I�/soc/qdss/tpath_aon_cam_noc I�/soc/qdss/tpath_aoc J/soc/qdss/tpath_swm_etm J/soc/funnel@10041000 J /soc/funnel@10B04000 J%/soc/funnel@10B44000 J./soc/funnel@10B50000 J7/soc/tpda@10B47000 J=/soc/tpda@10B53000 JF/soc/tpda@10B55000 =/soc/tnoc@10B31000 9 JP/soc/kernel_test_devices@0/interrupt-controller@10140000 JU/soc/systemcache@24800000 Jb/soc/ibi_ssc_0_cfg@7500000 Jp/soc/ibi_ssc_1_cfg@7510000 J~/soc/ibi_ssc_2_cfg@7520000 J�/soc/ibi_ssc_3_cfg@7530000 J�/soc/ibi_ssc_4_cfg@7540000 J�/soc/ibi_ssc_5_cfg@7550000 J�/soc/ibi_ssc_6_cfg@7560000 J�/soc/ibi_ssc_7_cfg@7570000 J�/soc/ibi_ssc_8_cfg@7580000 J�/soc/ibi_ssc_9_cfg@7590000 J�/soc/ibi_top_0_cfg@EC90000 J�/soc/ibi_top_1_cfg@ECA0000 K
/soc/ibi_top_2_cfg@ECB0000 K/soc/ibi_top_3_cfg@ECC0000 K&/soc/ibi_top_4_cfg@ECD0000 K4/soc/ibi_top_5_cfg@ECE0000
KB/soc/vdd_mxa
KJ/soc/vdd_mxc KR/soc/vdd_cx KY/soc/vdd_lpi_mx Kd/soc/vdd_lpi_cx Ko/sw model compatible #address-cells #size-cells proc-name chip-info spmi-bus0 spmi-bus1 phandle reg reg-names #clock-cells supported-hosts host remote-host fifo-size mtu-size irq-out qos-max-rate channel-name mailbox-area-size-bytes master-mailbox-size-bytes max-tx-pending-items is-master mailbox-desc-start host-name id transport remote-ss ch-name options priority stack-size intents tx-channel rx-channel host-id fflags max-entries dest proc irq core-top-csr-str tcsr-base mutex-offsets-data wonce-offsets client protocol-name protocol-idx interrupt-parent interrupts #signals client-mapping offset out-mask ngpios width qcom,strongpull egpio gpio-controller #gpio-cells interrupt-types interrupt-names summary-targetproc global-ctxt-name mux config qcom,sleep-config timer-name timer-freq timer-num timer-interrupt use-interrupt sid mid pmic bid therm-tbl label hw-ch hw-settle avg-sp dec-ratio cal-method scaling scale-fcn pull-up asid int-table pmic-sid gpio-num arr_id hw-common-params adctm-hw-params trip-range base_port num_ports atid sync_period lpi_funnel lpi_funnel_port port_ddr_lpi_tnoc dbg_regs pwrdbg_ctrl_reg cti_channels cti_triggers tpath tstype tpdm_name tpda tpda_port dataset cmb_size tpda_name port_occupied_mask tnoc_id tnoc_funnel_name cti_name interrupt-controller #interrupt-cells message llcc-common-reg llcc-lcp-reg disable-wrsc-on-preload lpi-base scid ibi_id gpii gpii_irq mgr_irq status gsi_pa tcsr_addr tcsr_gpii_offset tcsr_irq gpii_interrupts num_gpii active clock-names clocks qup_id qup_common_offset se_wrapper_base_offset core_frequency qup_flags num_se sdc_gpii_list core_offset ibi_instance se_flags se_index FIFO_MODE protocol_supported interface_supported num_gpiis ring_size_multiplier core_irq pdc_irq parent_wakeup_gpio shared_se od_frequency i2c_hs_i3c_src_freq is_pipeline_enable pinctrl-names pinctrl-0 pinctrl-1 pinctrl-2 pinctrl-3 pinctrl-4 pinctrl-5 pinctrl-6 pinctrl-7 pinctrl-8 pinctrl-9 pinctrl-10 pinctrl-11 i2c_hub num_top_qups irq_num qup0_cfg qup1_cfg qup2_cfg uStructVer pszInstName uaMasterEA pszHwioBase uHwioBaseOffset uHwioBase hBamDev uIntId uBamIntId uMyEE smbus_clk smbus_data uGpioIntNum uaNumEndPoints uaVoltageVote bIsLpiTlmm LA uaEA uDataLineMask num_device_props tlmm_name_str svs_npa_str is_master default_clock_gear prog_bam_trust island_vote subsystem_sleep_vote tlmm_offset tlmm_val svs_npa use_gpio_int log_level no_retention num_local_ports local_port_base local_channel_base shared_channel_base num_local_counters is_lpm_used_for_mgr_bam_trans lpm_mgr_sb_region_base lpm_mgr_sb_region_size is_lpm_sat_sb_region_dump_enable lpm_sat_sb_region_base lpm_sat_sb_region_size ee_assign rev MmpmCoreIdType MmpmCoreInstanceIdType pClientName pwrCtrlFlag callBackFlag MMPM_Callback cbFcnStackSize regulator-name regulator-min-microvolt regulator-max-microvolt regulator-init-microvolt qcom,resource-name qcom,all-pd-regulator qcom,lpr-enable qcom,drv-id num_ssc_qup ibi_base protocol se_island_config tre_list_size ibi_se_index se_mode load_fw dfs_mode test_config test_bool1 test_bool2 test_ver test_uint8_list test_uint16 test_uint32 test_uint32_list test_uint64 test_string test_uint8 test_uint8_list_empty test_uint16_list test_uint16_list_empty test_uint32_list_empty test_uint64_list test_uint64_list_empty reg_alt PD_indicator test_oem_entry jeita-alg afp-cold-degc jeita-hard-cold-degc jeita-hard-hot-degc jeita-hard-hys-degc afp-hot-degc vflt-nominal-mv fcc-nominal-ma die-temp-cfg conn-temp-cfg en-aged-batt-comp rechg-iterm rechg-soc-delta-pct rechg-delta-vflt-mv vflt-comp-mv iterm-comp-ma en-wls wls-pre-regulator boost-src otg-boost-src wls-tx-cfg ext-gpio-boost usb-switch wls-load-switch wls-to-vin en-apsd-pwr qc-det-cfg dam-hc-override apsd-rerun-cfg dam-aicl-cfg en-ufcs en-dam-qc-usb slave-addr force-eoc-5v ptm-cfg-1s en-inov-chg-5v se-idx se-int-num se-flags tlmm-gpio-num pmic-gpio-num pmic-idx ufcs-flags snk-max-mv snk-max-ma vdm-limit-cfg wd-timer-cfg-ms wd-timer-pet-ms hw-version sw-version en-chg-lmt charge-end-threshold charge-start-threshold smb-intf-cfg i2c-instance smb-m-addr smb-s-addr smb-r-addr struct-ver plat-id is-test-mode test-mode-flag chg-heartbeat-timer-ms dischg-heartbeat-timer-ms poll-timer-ms chg-done-timer-ms vbatt-avg-sample-size en-linear-soc soc-conv-pt min-linear-soc wd-bark-timer-ms wd-bite-timer-ms gen-test-interface en-stepchg-jeita iterm-ma bmd-src-sel en-direct-chg precharge-curr-step-size en-beh beh-debug-board beh-normal-batt beh-smart-auth-state beh-unknown-state beh-batt-miss-state beh-invalid-state beh-afp-state dbg-rid-cfg normal-rid-cfg smart-rid-cfg chg-table-max esd-timer-ms esd-voltage-mv esd-init-soc en-batt-auth batt-auth-timeout-s batt-auth-checktimer-ms batt-unauth-charging-action batt-auth-public-key-len batt-auth-challenge-len batt-auth-response-len batt-auth-public-key en-batt-auth-bsi-chip attributes conn-num en-alt-mode bc-ver pd-ver typec-ver op-mode provider consumer dfp-swap-en ufp-swap-en src-swap-en snk-swap-en ext-op-mode port-idx en-pd en-pan pd-rev snk-cap-size snk-caps-pdos snk-max-voltage-mv snk-max-current-ma snk-pwr-eval-alg snk-max-pwr-uw src-max-voltage-mv src-max-current-ma src-max-pwr-uw src-cap-size src-caps-pdos en-pps en-vconn-swap en-fr-swap en-vdm-altmode en-vdm-cable-discovery slow-charge-thr mismatch-thr drp-pps-support mpm-snk-time-ms mpm-src-time-ms pan-ack-tmout-ms batt-cap-vid batt-pid src-cap-ext-cfg en-lpd en-fod rsbu-thr-kohm holdoff-time-ms cooldown-time-s mitigation-current-ma sink-periodic-lpd compbox-imp-cfg-size sbu1-imp-kohm sbu2-imp-kohm cc1-imp-kohm cc2-imp-kohm dp-imp-kohm dm-imp-kohm fod-cc1-imp-kohm fod-cc2-imp-kohm port-role en-trysnk en-trysrc dam-gpio-en dam-pmic-idx dam-pmic-gpio-num en-dam-src src-rp-val en-audio-adap usb-switch-notify-en vbus-rampdown-wait-ms vbus-default-mv vbus-init-step-mv vconn-src-sel vdo-header cert-state product dfp-product ufp-product sop-discover-resp vph-min-mv fvss-entry-delta-mv fvss-vbatt-filt-tau-us fcss-entry-delta-ma fcss-ibatt-filt-tau-us hold-soc-1-pct cl-learn-min-delta-soc cl-wt-learn soh-tbat-range-degc soh-soc-range ignore-shdn-soc-param pon-debug-fifo-count hpm-fifo-len vbatt-empty-1s vbatt-empty-2s en-split-profile seperate-2p-batt vbat-cut-off-mv ibatt-cutoff-min-ma rconn-mohm ibatt-full-delta-ma image_idx eic_crash_enable eic_crash_type eic_crash_delay pd_timeout_exit_msec threshold_timeout_sec num_pdrs_log pd_binary_local_path pd_binary_remote_path pd_name pd_mon_install_attr pd_mon_image_sw_id subdomain_name pd_mon_restart_enable pd_mon_dump_disable rcinit_term_err_fatal_enable rcinit_term_timeout rcinit_term_timeout_group_0 rcinit_term_timeout_group_1 rcinit_term_timeout_group_2 rcinit_term_timeout_group_3 rcinit_term_timeout_group_4 rcinit_term_timeout_group_5 rcinit_term_timeout_group_6 rcinit_term_timeout_group_7 rcinit_term_latency_enable servreg_local_domain servreg_soc_name servreg_domain_name servreg_subdomain_name servreg_qmi_instance_id ssctl_srv sys_m_smem_ssr_res wdog_nmi_time wdog_bite_time wdog_bark_time wdog_status wdog_ctl wdog_bite_nmi wdog_reset wdog_nmi_time_data_bmsk wdog_bite_time_data_bmsk wdog_bark_time_data_bmsk wdog_ctl_wdog_to_nmi_en_bmsk wdog_ctl_wdog_to_nmi_en_shft wdog_ctl_enable_bmsk wdog_ctl_enable_shft wdog_reset_wdog_reset_shft image_id service_id qdss_service_id pram_name pt_name wdog_irq_num err_irq_num code_ram_addr data_ram_addr code_ram_size data_ram_size pram_addr ssc_sdc_physpool_addr ssc_sdc_physpool_size ipcmem_physpool_addr ipcmem_physpool_size diag_cmd_request_f diag_start_stress_test_f diag_stress_test_loopback diag_legacy_health_count_base diag_get_max_req_pkt_len diag_delay_health_count_base diag_dcm_cmd_reg_test_base diag_ulogdiag_processor_id diag_subsys_id_base diag_flow_control_count_base diag_dsm_chained_count_base diag_get_cmd_reg_tbl diag_subsys_mask_retrieval_base diag_f3_trace_set_config diag_tx_mode_config diag_stress_test_delayed_rsp diag_drop_threshold_config diag_query_enable diag_get_time_api diag_get_drop_per diag_uimage_health_stats diag_start_stress_test_adv_f diag_health_stats_base diag_get_set_drain_param diag_set_drain_prop diag_health_report_config diag_get_set_client_settings diag_lock_buffer_api diag_instance_id_base diag_err_ulog_size diag_debug_ulog_size diag_cmd_ulog_size diag_data_ulog_size diag_qdss_ulog_size diag_ctrl_ulog_size diag_listener_ulog_size diag_sendbuf_dbg_ulog_size diag_mpd_drain_timer_len diag_mpd_buf_commit_thresh_per diag_mpd_buf_drain_thresh_per diag_event_timer_len diag_event_rpt_pkt_len_size diag_event_rpt_pkt_size diag_drain_timer_len diag_event_send_max diag_event_heap_size diag_ctrl_send_buf_size diag_ctrl_read_buf_size diag_cmd_read_buf_size diag_event_sec_heap_size diag_dci_read_buf_size diag_rsp_heap_size diag_heap_size diag_f3_trace_buf_size diag_buf_size diag_rsp_alloc_retry_timer_len diag_mask_notify_timer_len diag_tx_sleep_threshold_default diag_tx_sleep_time_default diag_core_pd_drain_threshold diag_sio_timeout_timer_len diag_cmd_read_tout_timer_len diag_max_active_listeners diag_many_drain_per_mark diag_few_drain_per_mark diag_hdlc_pad_len diag_stress_task_sleep_complete diag_buf_commit_threshold diag_buffer_default_lock_state diag_drop_flow_cnt_incr diag_drop_per_step_max diag_drop_per_threshold_max diag_deferrable_timer diag_deferrable_timer_ex diag_send_data_buf_size_max diag_min_send_data_size diag_msg_fmt_str_arg_size diag_event_rpt_pkt_len_size_nrt diag_event_rpt_pkt_size_nrt diag_event_send_max_nrt diag_event_timer_len_nrt diag_tx_sleep_threshold_nrt diag_tx_sleep_time_nrt diag_drain_timer_len_nrt diagbuf_commit_threshold_nrt diag_mpd_commit_thresh_nrt_per diag_uimage_drain_timer_len diag_uimage_buf_high_per_wm diag_uimage_f3_trace_buf_size diag_uimage_pool diag_uimage_test_pool diag_early_log_control diag_early_log_mask diag_early_event_mask diag_early_message_mask diag_f3_trace_control diag_f3_trace_detail_mask diag_f3_trace_version GlbCtxtHWMutexNumber THREAD_NUMBER OVERHANG_VOTE_TIMEOUT_MS DEBUG_LEVEL baseAddr physAddr coreId pwrDomain coreClockInstances masterBusPortInstances slaveBusPortInstances numInstances memId clkId clkType clkCntlType clkName clkSrcId memoryId portConnection busClk regProgClocks icbarbMaster accessPort icbarbSlave masterPort slavePort pwrDomainName pwrDomainType intrReinitTrigger intrReinitDone securityClocks clientNum routes hw_instance masterIcbPort slaveIcbPort min index0 index1 index2 index3 index4 index5 index6 index7 index8 index9 index10 llccs scid-mapping-reg clients dump-pools gcc lpass_aon_cc lpass_aon_mx_cc lpass_audio_cc lpass_core_cc lpass_lpmla_cc scc lpass_cesta ipcc_mproc ipcc_compute_l0 ipcc_compute_l1 ipcc_periph ipcc_fence ipcc_legacy tlmm qup2_se0_l0 ibi_i3c_qup2_se0_sda qup2_se0_l1 ibi_i3c_qup2_se0_scl qup2_se0_l2 qup2_se0_l3 qup2_se1_l0 ibi_i3c_qup2_se1_sda qup2_se1_l1 ibi_i3c_qup2_se1_scl qup2_se1_l2 qup2_se1_l3 qup2_se2_l0 ibi_i3c_qup2_se2_sda qup2_se2_l1 ibi_i3c_qup2_se2_scl qup2_se2_l2 qup2_se3_l0 ibi_i3c_qup2_se3_sda qup2_se2_l6 qup2_se3_l1 ibi_i3c_qup2_se3_scl qup2_se2_l4 qup2_se3_l2 qup2_se2_l3 qup2_se3_l3 qup2_se2_l5 qup2_se4_l0 qup2_se4_l1 qup2_se4_l2 qup2_se4_l3 qup2_se5_l0 qup2_se5_l1 qup2_se5_l2 qup2_se5_l3 qup2_se5_l6 qup2_se6_l0 qup2_se6_l1 qup2_se6_l2 qup2_se6_l3 qup2_se7_l0 ibi_i3c_qup2_se7_sda qup2_se7_l1 ibi_i3c_qup2_se7_scl qup2_se7_l2 qup2_se7_l3 qup1_se0_l0 ibi_i3c_qup1_se0_sda qup1_se0_l1 ibi_i3c_qup1_se0_scl qup1_se0_l2 qup1_se0_l3 qup1_se1_l0 ibi_i3c_qup1_se1_sda qup1_se1_l1 ibi_i3c_qup1_se1_scl qup1_se1_l2 qup1_se1_l3 qup1_se2_l0 qup1_se2_l1 qup1_se2_l2 qup1_se2_l3 qup1_se3_l0 qup1_se3_l1 qup1_se3_l2 qup1_se3_l3 qup1_se4_l0 ibi_i3c_qup1_se4_sda qup1_se4_l1 ibi_i3c_qup1_se4_scl qup1_se4_l2 qup1_se4_l3 qup1_se5_l0 qup1_se5_l1 qup1_se5_l2 qup1_se5_l3 qup1_se6_l0 qup1_se6_l1 qup1_se6_l2 qup1_se6_l3 qup1_se7_l0 qup1_se7_l1 qup1_se7_l2 qup1_se7_l3 qup1_se2_l4 qup1_se2_l5 qup1_se2_l6 top_qup1_se0_i2c_active top_qup1_se0_i2c_sleep top_qup1_se0_i3c_active top_qup1_se0_i3c_sleep top_qup1_se0_i3c_ibi_active top_qup1_se0_i3c_ibi_sleep top_qup1_se0_spi_active top_qup1_se0_spi_sleep top_qup1_se0_uart_active top_qup1_se0_uart_sleep top_qup1_se1_i2c_active top_qup1_se1_i2c_sleep top_qup1_se1_i3c_active top_qup1_se1_i3c_sleep top_qup1_se1_i3c_ibi_active top_qup1_se1_i3c_ibi_sleep top_qup1_se1_spi_active top_qup1_se1_spi_sleep top_qup1_se1_uart_active top_qup1_se1_uart_sleep top_qup1_se2_i2c_active top_qup1_se2_i2c_sleep top_qup1_se2_spi_active top_qup1_se2_spi_sleep top_qup1_se2_uart_active top_qup1_se2_uart_sleep top_qup1_se3_i2c_active top_qup1_se3_i2c_sleep top_qup1_se3_spi_active top_qup1_se3_spi_sleep top_qup1_se3_uart_active top_qup1_se3_uart_sleep top_qup1_se4_i2c_active top_qup1_se4_i2c_sleep top_qup1_se4_i3c_active top_qup1_se4_i3c_sleep top_qup1_se4_i3c_ibi_active top_qup1_se4_i3c_ibi_sleep top_qup1_se4_spi_active top_qup1_se4_spi_sleep top_qup1_se4_uart_active top_qup1_se4_uart_sleep top_qup1_se5_i2c_active top_qup1_se5_i2c_sleep top_qup1_se5_spi_active top_qup1_se5_spi_sleep top_qup1_se5_uart_active top_qup1_se5_uart_sleep top_qup1_se6_i2c_active top_qup1_se6_i2c_sleep top_qup1_se6_spi_active top_qup1_se6_spi_sleep top_qup1_se6_uart_active top_qup1_se6_uart_sleep top_qup1_se7_i2c_active top_qup1_se7_i2c_sleep top_qup1_se7_spi_active top_qup1_se7_spi_sleep top_qup1_se7_uart_active top_qup1_se7_uart_sleep top_qup2_se0_i2c_active top_qup2_se0_i2c_sleep top_qup2_se0_i3c_active top_qup2_se0_i3c_sleep top_qup2_se0_i3c_ibi_active top_qup2_se0_i3c_ibi_sleep top_qup2_se0_spi_active top_qup2_se0_spi_sleep top_qup2_se0_uart_active top_qup2_se0_uart_sleep top_qup2_se1_i2c_active top_qup2_se1_i2c_sleep top_qup2_se1_i3c_active top_qup2_se1_i3c_sleep top_qup2_se1_i3c_ibi_active top_qup2_se1_i3c_ibi_sleep top_qup2_se1_spi_active top_qup2_se1_spi_sleep top_qup2_se1_uart_active top_qup2_se1_uart_sleep top_qup2_se2_i2c_active top_qup2_se2_i2c_sleep top_qup2_se2_spi_active top_qup2_se2_spi_sleep top_qup2_se2_uart_active top_qup2_se2_uart_sleep top_qup2_se3_i2c_active top_qup2_se3_i2c_sleep top_qup2_se3_spi_active top_qup2_se3_spi_sleep top_qup2_se3_uart_active top_qup2_se3_uart_sleep top_qup2_se4_i2c_active top_qup2_se4_i2c_sleep top_qup2_se4_spi_active top_qup2_se4_spi_sleep top_qup2_se4_uart_active top_qup2_se4_uart_sleep top_qup2_se5_i2c_active top_qup2_se5_i2c_sleep top_qup2_se5_spi_active top_qup2_se5_spi_sleep top_qup2_se5_uart_active top_qup2_se5_uart_sleep top_qup2_se6_i2c_active top_qup2_se6_i2c_sleep top_qup2_se6_spi_active top_qup2_se6_spi_sleep top_qup2_se6_uart_active top_qup2_se6_uart_sleep top_qup2_se7_i2c_active top_qup2_se7_i2c_sleep top_qup2_se7_i3c_active top_qup2_se7_i3c_sleep top_qup2_se7_i3c_ibi_active top_qup2_se7_i3c_ibi_sleep top_qup2_se7_spi_active top_qup2_se7_spi_sleep top_qup2_se7_uart_active top_qup2_se7_uart_sleep lpi_tlmm slimbus_clk slimbus_data slimbus_default_gpio_cfg ssc_tlmm ssc_qupv3_se0_0 ssc_qupv3_se0_1 ssc_qupv3_se1_0 ssc_qupv3_se1_1 ssc_qupv3_se2_0 ssc_qupv3_se2_1 ssc_qupv3_se2_2 ssc_qupv3_se4_4 ssc_qupv3_se2_3 ssc_qupv3_se4_5 ssc_qupv3_se3_0 ssc_qupv3_se2_4 ssc_qupv3_se3_1 ssc_qupv3_se2_5 ssc_qupv3_se4_0 ssc_qupv3_se4_1 ssc_qupv3_se4_2 ssc_qupv3_se4_3 ssc_qupv3_se5_2 ssc_qupv3_se5_0 ssc_qupv3_se1_2 ssc_qupv3_se5_3 ssc_qupv3_se5_1 ssc_qupv3_se1_3 ssc_qupv3_se6_0 ssc_qupv3_se6_2 ssc_qupv3_se10_2 ssc_qupv3_se6_1 ssc_qupv3_se6_3 ssc_qupv3_se10_3 ssc_qupv3_se7_2 ssc_qupv3_se7_0 ssc_qupv3_se7_3 ssc_qupv3_se7_1 ssc_qupv3_se8_0 ssc_qupv3_se8_1 ssc_qupv3_se9_0 ssc_qupv3_se9_1 ssc_qupv3_se10_0 ssc_qupv3_se10_1 ssc_qupv3_se11_0 ssc_qupv3_se11_1 ssc_qupv3_se11_2 ssc_qupv3_se11_3 ssc_qupv3_se12_0 ssc_qupv3_se12_1 ssc_qupv3_se13_0 ssc_qupv3_se13_1 ssc_qupv3_se13_2 ssc_qupv3_se13_3 ssc_qupv3_se14_0 ssc_qupv3_se14_1 qup_ssc0_se0_i2c_active qup_ssc0_se0_i2c_sleep qup_ssc0_se0_i3c_active qup_ssc0_se0_i3c_sleep qup_ssc0_se0_i3c_ibi_active qup_ssc0_se0_i3c_ibi_sleep qup_ssc0_se1_i2c_active qup_ssc0_se1_i2c_sleep qup_ssc0_se1_i3c_active qup_ssc0_se1_i3c_sleep qup_ssc0_se1_i3c_ibi_active qup_ssc0_se1_i3c_ibi_sleep qup_ssc0_se1_spi_active qup_ssc0_se1_spi_sleep qup_ssc0_se1_spi_3w_active qup_ssc0_se1_spi_3w_sleep qup_ssc0_se1_uart_active qup_ssc0_se1_uart_sleep qup_ssc0_se2_i2c_active qup_ssc0_se2_i2c_sleep qup_ssc0_se2_i3c_active qup_ssc0_se2_i3c_sleep qup_ssc0_se2_i3c_ibi_active qup_ssc0_se2_i3c_ibi_sleep qup_ssc0_se2_spi_active qup_ssc0_se2_spi_sleep qup_ssc0_se2_spi_3w_active qup_ssc0_se2_spi_3w_sleep qup_ssc0_se2_uart_active qup_ssc0_se2_uart_sleep qup_ssc0_se3_i2c_active qup_ssc0_se3_i2c_sleep qup_ssc0_se3_i3c_active qup_ssc0_se3_i3c_sleep qup_ssc0_se3_i3c_ibi_active qup_ssc0_se3_i3c_ibi_sleep qup_ssc0_se4_i2c_active qup_ssc0_se4_i2c_sleep qup_ssc0_se4_spi_active qup_ssc0_se4_spi_sleep qup_ssc0_se4_spi_3w_active qup_ssc0_se4_spi_3w_sleep qup_ssc0_se4_uart_active qup_ssc0_se4_uart_sleep qup_ssc0_se5_i2c_active qup_ssc0_se5_i2c_sleep qup_ssc0_se5_i3c_active qup_ssc0_se5_i3c_sleep qup_ssc0_se5_i3c_ibi_active qup_ssc0_se5_i3c_ibi_sleep qup_ssc0_se5_spi_active qup_ssc0_se5_spi_sleep qup_ssc0_se5_spi_3w_active qup_ssc0_se5_spi_3w_sleep qup_ssc0_se5_uart_active qup_ssc0_se5_uart_sleep qup_ssc0_se6_i2c_active qup_ssc0_se6_i2c_sleep qup_ssc0_se6_i3c_active qup_ssc0_se6_i3c_sleep qup_ssc0_se6_i3c_ibi_active qup_ssc0_se6_i3c_ibi_sleep qup_ssc0_se6_spi_active qup_ssc0_se6_spi_sleep qup_ssc0_se6_spi_3w_active qup_ssc0_se6_spi_3w_sleep qup_ssc0_se6_uart_active qup_ssc0_se6_uart_sleep qup_ssc0_se7_i2c_active qup_ssc0_se7_i2c_sleep qup_ssc0_se7_spi_active qup_ssc0_se7_spi_sleep qup_ssc0_se7_spi_3w_active qup_ssc0_se7_spi_3w_sleep qup_ssc0_se7_uart_active qup_ssc0_se7_uart_sleep qup_ssc0_se8_i2c_active qup_ssc0_se8_i2c_sleep qup_ssc0_se8_i3c_active qup_ssc0_se8_i3c_sleep qup_ssc0_se8_i3c_ibi_active qup_ssc0_se8_i3c_ibi_sleep qup_ssc0_se9_i2c_active qup_ssc0_se9_i2c_sleep qup_ssc0_se9_i3c_active qup_ssc0_se9_i3c_sleep qup_ssc0_se9_i3c_ibi_active qup_ssc0_se9_i3c_ibi_sleep qup_ssc0_se10_i2c_active qup_ssc0_se10_i2c_sleep qup_ssc0_se10_spi_active qup_ssc0_se10_spi_sleep qup_ssc0_se10_spi_3w_active qup_ssc0_se10_spi_3w_sleep qup_ssc0_se10_uart_active qup_ssc0_se10_uart_sleep qup_ssc0_se11_i2c_active qup_ssc0_se11_i2c_sleep qup_ssc0_se11_spi_active qup_ssc0_se11_spi_sleep qup_ssc0_se11_spi_3w_active qup_ssc0_se11_spi_3w_sleep qup_ssc0_se11_uart_active qup_ssc0_se11_uart_sleep qup_ssc0_se12_i2c_active qup_ssc0_se12_i2c_sleep qup_ssc0_se13_i2c_active qup_ssc0_se13_i2c_sleep qup_ssc0_se13_i3c_active qup_ssc0_se13_i3c_sleep qup_ssc0_se13_i3c_ibi_active qup_ssc0_se13_i3c_ibi_sleep qup_ssc0_se13_spi_active qup_ssc0_se13_spi_sleep qup_ssc0_se13_spi_3w_active qup_ssc0_se13_spi_3w_sleep qup_ssc0_se13_uart_active qup_ssc0_se13_uart_sleep qup_ssc0_se14_i2c_active qup_ssc0_se14_i2c_sleep qup_ssc0_se14_i3c_active qup_ssc0_se14_i3c_sleep qup_ssc0_se14_i3c_ibi_active qup_ssc0_se14_i3c_ibi_sleep SystemTimer WakeUpTimer pmic0 therm_table tpath_lpi_tpda tpath_rscc_tpda tpath_audio_tpda tpath_lpi_stm tpath_lpi_etm tpath_stm tpath_sdc_itm tpath_lpi_noc tpath_aon_cam_noc tpath_aoc tpath_swm_etm in_fun0 swao_fun lpi_fun0 lpi_fun1 lpass lpi_rscc lpi_audio intc systemcache0 ibi_ssc_0_cfg ibi_ssc_1_cfg ibi_ssc_2_cfg ibi_ssc_3_cfg ibi_ssc_4_cfg ibi_ssc_5_cfg ibi_ssc_6_cfg ibi_ssc_7_cfg ibi_ssc_8_cfg ibi_ssc_9_cfg ibi_top_0_cfg ibi_top_1_cfg ibi_top_2_cfg ibi_top_3_cfg ibi_top_4_cfg ibi_top_5_cfg vdd_mxa vdd_mxc vdd_cx vdd_lpi_mx vdd_lpi_cx sw �
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